Design-to-Verification Software

The HDL (hardware description language) Designer series has been extended to provide a platform for implementing SystemVerilog. The HDL Designer series, used to accelerate register transfer level (RTL) design reuse and optimize design creation, synthesis, and verification processes for complex ASIC and field-programmable gate array (FPGA) designs, formulates an optimum design-to-verification environment for creating and managing complex designs using VHDL, C/C++, PSL, Verilog, mixed-languages, and now, SystemVerilog. Unlike traditional HDLs, SystemVerilog introduces an object-oriented design style that offers many new language features. The HDL Designer Series with SystemVerilog provides a unified environment for all HDLs, while taming the complexity of object-oriented programming. As a result, it improves designer productivity. Mentor Graphics Corp., Wilsonville, OR;


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.