December 10, 2007 – IBM says it has fabricated 32nm chips using a high-k/metal gate (gate-first) process in SRAM chips, which it says shrinks the chips size by up to 50%, and saves about 45% total power. The technology is expected to be available in 2H09.

Earlier this year, also at the same time Intel made known some initial details of its 45nm HK+MG process, IBM and its Common Platform Alliance released a statement indicating that they, too, were in the final stages of tinkering with the technology.

Now, IBM is trying to similarly keep alongside Intel, which is disclosing more details of its 45nm HK+MG work at this week’s IEDM. The partners say they have fabricated low-power foundry CMOS technology high-k “gate-first approach, in 32nm ultradense SRAM, with <0.15micron cell sizes. Total chip power consumption is reduced by as much as 45% compared with previous generation technology, they add.

The Common Platform Alliance partners say they have incorporated the high-k technology into a new generation of silicon-on-insulator (SOI) using 32nm processes, improving transistor speeds by up to 30%, and with lower voltages.

Demonstrating the high-k gate-first approach in a manufacturing environment “provides clients with a simple, scalable pathway to incorporating the high-k material innovation in semiconductor development without introducing additional design complexity,” said Gary Patton, VP of IBM’s Semiconductor R&D Center, in a statement.