IEDM news: NEC’s low-k Cu-interconnect structure, and “channel-engineering” designs

December 16, 2007 – At this year’s IEDM, NEC and NEC Electronics unveiled new design technology to optimize ultrashallow-junction channel structures in 32nm-and beyond LSIs, as well as a new composite film to enable a “full low-k” Cu interconnect structure with k reduced nearly a third compared to conventional barrier dielectrics.

In their first paper, NEC and NEC Electronics discussed a new silica-carbon composite (SCC) film that establishes “an ultimate full-low-k Cu interconnect structure” to reduce active power consumption in LSI interconnects, attributed to manipulating the molecular structure and novel plasma-enhanced deposition technology.

The new low-k barrier dielectric SCC film — with k decreased to 35% that of conventional barrier dielectrics — has a composite structure of unsaturated C=C molecular bonds and the conventional silica backbone structure to prevent Cu diffusion into the interlayer dielectric films. The SCC film blocks migration of the Cu atoms (likely captured by the unsaturated carbon bonds). The FLK Cu interconnect incorporates a seamless stack of molecular pore stack low-k film with stable sub-nm-sized pores, deposited continuously on the SCC film on top of the underlying Cu lines, and SCC barrier dielectrics on the Cu lines.

Insulation reliability was deemed “excellent” (measured through a special stabilization process of the Cu metal surface), even after reducing film thickness to several 10s of a nanometer, the companies said. Parasitic capacitance was reduced by 11% compared with low-k Cu interconnects without the SCC film, and reliability was said to be “improved,” though the firms provided no relative comparative value.

The structure is applicable not only to leading-edge CMOS devices (i.e. 32nm node), but also many other conventional CMOS devices for lower power consumption and high reliability — e.g. networking equipment such as broadband wireless terminal devices, multitask servers, and microcomputers for automotive applications, the firms said.

Part of this research was supported by the New Energy and Industrial Technology Development Organization (NEDO) under the MIRAI project.

Also at IEDM, NEC and NEC Electronics said they had developed new technology to visualize impurity distributions in transistors based on e-beam holography technology with “world-leading high spatial resolution.” E-beam holography detects slight perturbation in the wavelength of electrons that results from traversing through silicon crystal with different electrostatic potentials (e.g. n-type vs. p-type silicon), to obtain a nanometer-scale mapping of pn-junctions, the company explained, in a statement.

Addressing the problem of leakage current in advanced CMOS devices requires formation of ultrashallow junctions (USJ) in the channel regions of transistors, but these must be precisely structured to not only suppress leakage current but also prevent parasitic resistance that degrades device performance. That means designing optimum shapes for the USJ based on process simulations (TCAD), and also a highly accurate metrology technique to allow tuning of the process parameters by observing junction structures built into the device. From a process point of view, this requires an ion implantation technique to isolate impurity atoms only in the very shallow region from the surface of the silicon crystals, and an annealing technique with a thermal budget to achieve electrical activation of impurities without letting them redistribute through thermal diffusion.

In their research, the firms said they built pn-junctions with low resistance and very steep impurity profiles through two processes: cluster-ion implantation (suppressing the channeling effect for implanted impurity atoms), and diffusion-less high-temperature millisecond annealing (for impurity activation). To visualize cross-sectional potential distributions in the transistors, e-beam holography was applied with “world-leading spatial resolution” to enable calibration of TCAD results. Their work realizes shape control of the USJ and optimized fab processes, demonstrating that planar-bulk-type CMOS devices “can be miniaturized down to the 30nm generation, while maintaining good performance and suppressed leakage current.”


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