IEDM news: TSMC reports 32nm SRAM, sans HK+MG

December 10, 2007 – Top global foundry TSMC says it has developed a 2Mb SRAM test chip with 32nm process technologies that supports both analog and digital functionality — and doesn’t rely upon high-k gate dielectrics or metal gates. The foundry also said it has made a 0.15-sq. micron high-density SRAM cell using 193nm immersion lithography with double patterning.

The technology, optimized for low power, high density, and “manufacturing margins with optimal process complexity,” integrates high-density SRAM, low standby transistors, analog and RF functions, and copper and low-k interconnects. The company says it will provide complete digital, analog and RF functions, and high density memory capabilities at 32nm node.


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