by Debra Vogler, Senior Technical Editor, Solid State Technology
At next week’s IEDM 2007 conference in Washington, DC, IMEC is presenting a variety of papers that cover topics ranging from: PVD used for workfunction electrode metal in FinFETs; interactions between a capping layer, host dielectric, and workfunction metal that impacts threshold voltage; and using laser annealing in (gate-first) high-k/metal gate devices to achieve gate length scaling with no loss in drive current.
A paper by G. Vellianitis, et al., describes the results achieved by IMEC participants (NXP Semiconductors, TSMC, and Philips Research Europe), who used PVD to deposit the workfunction electrode metal in FinFETs that were conventionally fabricated without mobility boosters. Despite the poorer conformality of PVD compared to PEALD (plasma enhanced ALD), the group found neither scalability nor performance impact for both dielectric and gate electrode. IMEC has had a five-year ongoing FinFET program, but until this year only ALD had been used for the workfunction metals, noted Serge Biesemans, IMEC’s director of FEOL integration.
Another key finding in a paper by V.S. Chang et al. (IMEC, TSMC, ASM, Samsung, Infineon, Matsushita, and Aixtron) is the discovery of an interaction mechanism between a capping layer and a host dielectric, and between a capping layer and the workfunction metal. The interaction is apparent for both nMOS and pMOS gate stacks and the interaction results in a beneficial shift in V t .
According to Biesemans, a major question facing the industry is whether planar CMOS or a FinFET architecture will be used at 22nm. In a paper by I. Ferain et al., a group comprising IMEC, K.U. Leuven, Samsung, Aixtron, and TI essentially repeats the work of Chang’s group, except on FinFETs. Their conclusion is that either planar CMOS or FinFETs will work from a gate stack point of view. “There is no difference,” Biesemans told WaferNEWS.
A paper by Kubicek, et al. (IMEC, TSMC, Matsushita, Infineon, Samsung, NXP, and K.U. Leuven) will show how using laser annealing for junction activation in high-k/metal gate devices using a gate-first process provides good gate length scaling without a loss of drive current.
Heading into IEDM, it appears there will still be many options for materials and metals the industry will need to resolve over the next few years, and as Biesemans noted, the options selected will very likely depend on whatever is most cost-effective for a given company. The myriad choices will also continue to put the industry in a bind — “straining resources tremendously to try to keep a critical mass for each topic,” he explained. “There are a lot of options. Even for consortia, we can’t do it all; we have to make choices.”
Biesemans also believes that the future will bring a consolidation of the consortia with perhaps no more than two remaining to address all the industry’s challenges. Conversely, the business model of many research centers each working on a given topic would have a lot of overhead, he pointed out. IMEC has chosen to diversify and will continue to focus on logic, DRAM, and flash. — D.V.