by Debra Vogler, Senior Technology Editor, Solid State Technology
Intel execs revealed highlights from select papers the company will be presenting at IEDM, including some details about its 45nm HK+MG transistors that incorporate a redistribution layer as part of a 9-layer copper interconnect. Also featured is the company’s success in mitigating process variation to the extent that results in variation at 45nm is comparable to that achieved at 130nm. Additionally, quantum well FETs may be ready at ~2015 to extend Moore’s Law scaling.
Advancing technology with one step forward, three steps back
An invited paper (#18.2, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”) outlines how Intel is mitigating certain aspects of process variation in 45nm devices relative to past generations. The company will reveal some of the details behind how it has been able to achieve across-wafer and within-die variation at 45nm to levels comparable to variation at the 130nm generation.
“Although device dimensions continue to shrink each generation, Intel continues to optimize its layout and its design and process improvements to maintain, or even improve, process variation from generation to generation,” said Kelin Kuhn, Intel Fellow and presenter of this paper. “Much of the literature extrapolates from generation to generation and comes to the erroneous conclusion that Moore’s Law is going to end because the variation is getting so high,” she said. “Part of the function of this paper is to show no, that’s not true — we actively reduce variation each generation in order to keep it either constant, or better, each time around.”
To demonstrate Intel’s ability to maintain very low random variation, both across the die and across the entire wafer, Kuhn will describe one of the techniques the company uses to measure it: special ring-oscillator test structures. Random variation is measured by taking the difference between two adjacent test structures. She will also present data that illustrates that the variation at 45nm is comparable to what Intel achieved at 130nm.
Other data to be presented compares SRAM structures at 90nm, 65nm, and 45nm (see Fig. 1, below). In going from 90nm to 65nm, Intel used a design mitigation strategy by changing the cell geometry from a “tall” design to a “wide” design. This “significantly improves variation by aligning the poly in one direction and eliminating diffusion corners,” said Kuhn, noting that that this kind of design mitigation has been done by several other companies.
At 45nm, however, Intel uses a process mitigation strategy — i.e., changing the patterning process to create square endcaps that improve variation relative to rounded endcaps, which are characteristic of the design at 65nm. At 45nm, the poly achieved has no bubbles or variation. Many details of how Intel had to change the lithography to be compatible with the “wide” design process will remain proprietary, but some have been released previously, and additional examples will be shown at IEDM, Kuhn told WaferNEWS.
45nm HK+MG: Hitting all the high notes
In another widely anticipated paper (#10.2, “A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging) Intel VP Kaizad Mistry will show how the ninth layer of a 9-layer copper interconnect is used as a redistribution layer, able to achieve uniform power distribution across the die, thus eliminating voltage droops and current spikes associated with hot spots. The latest 45nm HK+MG transistor also uses Intel’s third generation strained silicon and features Intel’s Hf-based high-k gate dielectric and dual metal gate electrodes. Other process features to be discussed are the use of trench contacts instead of rectangular or round contacts, as well as lead-free packaging.
The redistribution layer, i.e., the 9th interconnect layer, is “very” thick, allowing for “very nice” on-die power distribution, Mistry told WaferNEWS. “The redistribution layer enables a more uniform current distribution across the die so that when a hot spot is drawing a lot of current, there isn’t a resultant voltage droop or current spike,” he explained. However, this redistribution layer does not deal with the thermal ramifications of a hot spot.
Mistry added that he will describe “in detail” the process flow to generate the high-k transistors, as well as some of the electrical characteristics that support a very high performance (very high drive current). He also will go into some of the details of how the company improved the strain process in going from 65nm to 45nm, the third generation of strained silicon.
According to Mistry, the benefits attained from Intel’s 45nm HK+MG and the enhanced strained silicon include a better than 10X reduction in gate leakage, 30% lower switching power over the prior generation, and, either a significant increase in performance (over 20% at the same leakage) or a reduction in leakage of 5X at the same performance or drive current (see Fig. 2, below). “This is a trade-off between leakage and drive current,” explained Mistry. “If you have a lower threshold voltage, you’ll get more drive current and more leakage