December 13, 2007 – The Semiconductor Research Corp. (SRC) and U. of Glasgow are partnering to identify “the best” p-channel material to scale MOSFET minimum feature sizes, including gate length, down to 8nm, possibly extending scaling for another 4-6 years beyond current projections.
Industry efforts have managed to improve switching speeds by nearly 20% annually, keeping scaling on the pace of Moore’s Law. But that pace is in danger of slowing down unless the industry can find and integrate new compound materials (e.g. InGaAs and others) to replace silicon as the channel region of the MOSFET, they explained, in a statement.
One of Glasgow’s research goals will be to “strain” p-type compound semiconductors similar to how performance enhancements have been realized in silicon, targeting yield mobilities of ~ 6000-50,000 cm2/Vs. That’s more than 10x the values achievable in silicon, which has the potential to significantly reduce switching speeds to produce faster chips, they claim.
The Glasgow team will collaborate with the Non-Classical Research Center (NCRC), launched in 2006 by SRC-GRC and led by U. of California-Santa Barbara, which is working on one half of the compound semiconductor challenge to provide a sharp increase in carrier velocities in the n-channel. The aim of the new work at Glasgow will be to complete the other half, identifying significantly improved velocities in the p-channel, also using compound elements.
The three-year project will begin in January with a total investment of $2.5 million, complementing and enhancing work already underway at Glasgow that is supported by the UK Engineering and Physical Sciences Research Council.
“Being able to utilize MOSFETs in compound semiconductors has been the elusive Holy Grail of scaling for 30 years,” said Jim Hutchby, senior scientist for the Global Research Collaboration (GRC), a unit of the SRC responsible for narrowing the options to keep scaling CMOS. “With what we expect to accomplish with the University of Glasgow, we may be only 2-3 years away from achieving that breakthrough.”
“We’re on our way to proving a new class of compound semiconductors that will provide better peak carrier velocities and lower voltages and allow the industry to supplement silicon’s critical paths for speed and power,” added Professor Iain Thayne, project leader for the Glasgow team.