by Brian Dance, European Contributing Editor, Solid State Technology
This year’s MEDEA+ annual forum in Budapest, Hungary (Nov. 26-28) reviewed final projects for the eight-year pan-European collaborate program for microelectronics R&D, set to expire in 2008. MEDEA+ has overseen three generations of CMOS technology, spanned 77 labeled projects involving 465 partner organizations from 22 countries and ~ 20,000 person-years, and enabled the European industry to become a world leader in such sectors as automotive electronics, smart card technology and image sensing.
Replacing MEDEA+ starting in January will be a new public-private partnership, “CATRENE” (Cluster for Application and Technology Research in Europe on NanoElectronics), a €6B (US ~$8.7B) four-year program (extendable another four years, as was MEDEA+) to take up the challenge of help Europe’s microelectronics industry develop and maintain strengths in nanoelectronics. R&D spending in technology and architecture will continue to rise, as R&D effort in Europe increases, with new applications addressing societal needs. Jozef Cornu, chairman of MEDEA+ and designated chairman of CATRENE, indicated that a first call for projects will be made by around March under Eureka project rules, based on a “bottom-up” procedure with experts judging the proposed projects’ quality and making recommendations for public funding.
Developments in lithography to support half-pitch resolutions down to 45nm and possibly 38nm appear well on track, according to ASML VP Paul van Wijnen, discussing the MEDEA+ 2T304 project LIQUID (LIthography based on Quite extreme Ultrahigh-NA 193 nm optical Immersion Development). He noted that a 1.35 NA system will be the industrial immersion standard, capable of 131 WPH throughput with 600 mm/s scan speed and 40nm resolution. NAND flash has been resolved down to 38nm, he noted, and work is underway for a new platform to push 193nm double patterning down to 32nm, with major changes including new high-speed high-acceleration stages and new technology to replace interferometer control.
No fluids suitable for immersion lithography have indices of over 1.7, but five fluids with refractive indices of about 1.65 look promising, with lower surface tension and higher viscosity than water, though their high temperature coefficients of refractive index necessitate temperature control to better than 1mK. Their latent heats are about a tenth of that of water. Work on 193nm based solutions for 38nm-32nm half-pitch resolutions has started using double patterning and liquids with high indices.
Increasing health care demands in aging worldwide populations is creating markets for devices such as “lab-on-a-chip” systems that will enable people to stay longer in their own homes, with remote monitoring where necessary. Laurent Malier, director of CEA-LETI, described a fully integrated point-of-care system for detecting nosocomial diseases. DNA can be directly grafted onto a CMOS ‘active pixel sensor,’ and chemiluminescence used to achieve a detection limit of <1pM. He cited cancer pre-diagnosis as an example of a possible future consumer application, detecting metabolic changes by the presence of specific volatile organic compounds in breath using very sensitive and selective chemical sensors.
The FDQ (Failure mechanism Driven Qualification) A407 project for reliability and analysis of electronic components was covered by Christian de Prost and Pascal Lecuyer of Atmel, with particular reference to the automotive and avionics sectors where the origins of failure causes are similar. They compared two imaging techniques for 65nm SRAM cells — a standard SEM picture lacked material details and showed no visible grains in a blurred image, whereas a He-ion microscope picture had sharp interfaces and showed W and Si grains.
A half-day ENIAC (European Nanoelectronics Initiative Advisory Council) Forum followed the MEDEA+ event, including details of a three year GOSSAMER project, a joint effort led by STMicroelectronics and Qimonda to investigate new architectures and materials for gigabyte non-volatile memories for mass storage, targeting the 32nm technology node, according to ST’s Livio Baldi. Strong gate and dielectric material innovations are needed so that charge trapping NAND can be considered as an alternative to floating gate at <40 nm. — B.D.