Designing Modern 3D Packages with Mixed Technology Content

BY PER VIKLUND, Mentor Graphics Corp.

Packaging technology has evolved over the years, transitioning into more of a revolution with the introduction of new packaging styles practically every month. Designers face designing extremely high-performance packages with mixed technology content such as high speed digital, analog, and RF. At the same time, density requirements force the use of 3D packaging technologies. As prototypes are a relic of the past when it comes to packaging design, early planning/evaluation, parasitic extraction simulation, and verification becomes more and more critical.

Clearly, the system packaging dilemma is a wide and complex topic. Therefore, investigating the complexity buried in the mere co-existence of multiple technologies in a chip package system requires a broad overview.

Multi-die Package Design Flow

Traditionally, chip designers design the chip core functionality and then hand it over to the I/O ring design teams (Figure 1). Ideally, these teams collaborate with package engineers on where to place specific signals and where to position power and ground. Gernerally, this is driven directly from the IC design teams.

Figure 1. Typical design flow for a multiple-die package design.
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Skilled engineers and a great deal of experience means that teams can still push their designs through, but it is becoming harder to succeed within reasonable time, which leads to unpredictable lead times and quality.


The latest trend, cross-discipline collaboration – known by some as “co-design” – carries different meaning for different people. Early co-design tools looked at how to let IC designers see the impact their actions had on the package to provide package-aware chip design. As system-in-package (SiP) becomes more popular, the same solutions are expanded to support multiple die, and assist design teams with various levels of optimization and a means to write the optimized results back to the chip-design environment.

SiPs have grown in complexity to a level where a different kind of co-design is needed. Figure 1 shows how the flow is broken at several places so that package-aware chip design is no longer enough. ASCII or spreadsheet files may be convenient, but in addition to being proprietary, it’s not a data format designed for the task it’s set to solve. Secondly, feedback of package information to chip design is poor, if at all available. Every I/O and power/ground decision at chip level impacts package design, and also PCB design. A way to analyze effects, optimize the situation, and feedback updates to chip design is needed that must be robust and secure.

Top Level Connectivity

Once there is a system-wide schematic (a classical symbol schematic, table driven, or a mix), the design can be considered at system level. Rather than deal with a single die, multiple die, the package, and even the PCB can all be in flux. Managing top-level package connectivity is necessary to allow system-wide optimization and management of design constraints.


The chip or package engineer typically designs package pin-out. The result affects chip, package, and board design; and ultimately system performance. The trend is going from optimizing I/Os only at chip level, to second-generation solutions that optimize chip-to-package design. System-level optimization would involve optimizing package pin-out against board and package content at the same time.

Package-on-package (PoP) devices with two sets of pin-outs – one on the bottom surface and one on the top surface – are also becoming more prevalent. Often, the top-level pin-out is fixed, dictated by JEDEC standards, while at other times it is flexible. Regardless, the top surface pin-out will impact the optimal bottom surface pin-out and, therefore, the chip I/O configuration and the bottom surface pin-out.


SiPs typically contain multiple circuit blocks of different technology such as RF or microwave, analog, and high speed digital. As package designs are dense, interaction between these systems is unavoidable. These cross-disciplinary aspects have to be handled early, when changes to the design are almost free.

However, at this point, so little is known about the design that all data entered for evaluation are pure assumptions. By estimating the total number of chip connections, early package feasibility studies can commence, using dummy die and connectivity to establish required package size and type. Having a rough idea of power consumption also allows for early power integrity planning at the package level.

As soon as there is a transition from “virtual prototyping” into “actual” design work, the cost increases rapidly as the design cycle progresses. Therefore, it may be beneficial to spend extra time in the early planning.

Incrementally Add Circuit Intelligence

When a signal list is available, it is possible to generate a preliminary pin-out driven from both chip and board. Import signal lists for each die, and then establish a top-level connectivity, analogous to a system schematic, but for the package alone. Table-driven interconnect editor-type tools are ideal for this purpose as they give an overview of the connectivity, and offer effective editing and signal manipulations for large signal counts.

At this time, chip design should have progressed enough to benefit being added to the package flow. Using standard data formats (Open Access, Lef/Def, HDL) incrementally adds real design knowledge to the process.

Evaluate Drivers and Topology

With signals in place, making initial signal I/O ring placement for each die can begin, as well as a preliminary power and ground port placement. Using SI and PI exploration tools, in combination with the SI models from the I/O library, makes it possible to run virtual SI/PI analysis where signal lengths and driver loads are estimated to see if the chosen I/O cell types will be capable of driving the given topology. The I/O ring with power/ground ports can now be fed back to IC design environments for each die for evaluation by the IC designer.

Stacked Die

Part of this iterative process is to evaluate different chip stacking configurations. It is often obvious which parts make sense to stack. What is less obvious is in what order and what rotation.

Figure 2. Correct-by-design 3D bond-out of two stacked die.
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It is necessary to run preliminary bond-outs (for wire-bonded die) already in the co-design process as wire bond patterns strongly affect several aspects of package design (Figures 2,3).

Figure 3. Three-dimensional view of the same bond out shown in Figure 2.
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Busses and differential signals require extra care, and sometimes evaluation of thermal aspects of a stacking configuration is required before the best option is settled upon. It may now be necessary to run yet another iteration of I/O optimization.

Virtual Becomes Actual

At this stage it makes sense to start the more detailed package design. What initially was just virtual data has gradually been replaced by real data.

Analysis between systems such as model the coupling of a high-speed clock line into an RF circuit or vice versa begins. Circuits are grouped together and pushed over an RF analysis tool, which generates an n-port S-parameter model to describe the interaction scenario. This information allows relocatation of circuits, changes in ground planes, RF routing etc.

Figure 4. Looping transpires between blocks in the flow until both sides are satisfied with the result.
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This process is different from the traditional flow. Beginning before data is actual, and as seen in Figure 4, looping between any blocks in the flow is allowed until both sides are satisfied with the result.


Using standard formats, such as Open Access and Lef/Def, this flow would work with almost any IC design tool on the market. By facilitating virtual prototyping and SI and PI analysis at the planning and co-design stage, it is possible to catch expensive issues before they happen and design correctly rather than being in a fix mode.

PER VIKLUND, director, IC packaging and RF system design division, may be contacted at Mentor Graphics (Scandinavia) AB Hassle Bösarp 12 Kista SE-27493 Sweden; +46/411 456 11; [email protected].


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