IITC event adding 3D, process details to interconnect agenda

Jan. 2, 2008 – Responding to feedback from attendees, this year’s IEEE International Interconnect Technology Conference (IITC: June 1-4, 2008) will widen its reach to include more content about 3D issues, and more details about the science behind the individual processes used in interconnect, from CMP to plating, etch, and patterning.

3D stacks was a hot topic at the 2007 IITC, but in the past 3D topics have been “scattered throughout the [IITC] program,” said Michael Shapiro, IITC 2008 publicity chair and senior technical staff member/chief engineer for 3D development at IBM, in a statement. “This year, we will have at least one whole session devoted to 3D, along with two invited speakers addressing important aspects of the topic, and our desire is to attract papers focusing on 3D silicon processes as opposed to packaging.”

Event organizers also are looking to go beyond traditional integration-focused topics with more papers discussing specific manufacturing issues, process modeling, and backend materials and unit processes — getting into the science behind the individual processes used in interconnect, such as CMP, plating, etch, and patterning. “For example, instead of a presentation offering an overview of how copper lines are integrated into a wiring structure, a presentation might actually describe the chemistry behind the copper plating process,” stated Shapiro.

Another big change to the IITC agenda is its venue — starting in 2009 the event will begin rotating among locations in Asia, Europe, and the US.


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