Jan. 21, 2008 – The two leading R&D centers for EUV lithography, IMEC in Europe and the U. of Albany’s College of Nanoscale Science and Engineering (CSNE), say they will jointly perform experiments for EUV in order to “demonstrate the practical feasibility of EUVL and build confidence in the technology for the 32nm half-pitch device node and below.”

First experiments will be done in Albany, focusing mainly on the system’s imaging capabilities, with other efforts looking at new materials and equipment technology. Future studies will be carried out at either location depending on throughput and tool availability. Key collaborators will include IBM and litho tool vendor ASML, which shipped its alpha EUV tools to both CSNE and IMEC in mid-2006.

“We have a unique opportunity to enable significant advances in EUVL technology that are vital to the manufacturing of future generations of nanoelectronics devices,” said Alain Kaloyeros, VP and chief administrative officer of the CNSE, in a statement.

EUV lithography is seen as a promising technology to help scale CMOS beyond the 32nm node, but “still major challenges need to be overcome,” stated Luc Van den hove, IMEC VP/COO. IMEC litho program director Kurt Ronse added that EUV is still in a development phase and alpha tools need upgrades, so opening up the facilities to the other for EUV experiments “can guarantee acceleration of EUV research to our industrial partners.”