Lithography workshop report: 193nm/DEDE for 32nm, still weighing 22nm options

by Griff Resor, Resor Associates and SST Editorial Advisory Board member

Immersion lithography was more than the central theme at the 2007 [formerly IEEE] Lithography Workshop (Dec. 9-13, Puerto Rico). For the first time in 50 years a tropical storm hit after the hurricane season, soaking many attendees trying to relax under the palm trees of the Rio Del Mar Resort.

Intel has started production at the 45nm node, with other chipmakers in-step or close behind. Surprisingly, Intel used an all dry processes for their 45nm node. They also used double patterning to create one layer (the gate layer).

With the 45nm node in production, this conference turned its attention to the 32nm and 22nm nodes. As one speaker observed, “Unfortunately, this time we know what our lithography tool will be: 193[nm] immersion.” EUV is not ready, so 193nm immersion tools must be stretched to make circuit patterns at the 32nm node.

Though it looked very carefully at inverse lithography, Intel has decided to use 193nm immersion and double patterning for the 32nm node. Speakers from nearly all the major IC companies reported the same general plan, but the details remain to be determined.

There will be many forms of double patterning, and each kind of chip (flash, DRAM, or logic) will probably have its own flavor. Spacer techniques can double the pitch, but asymmetrical spacer process errors generate image placement errors, and the spacer process appears to be overly complex. Double exposure, double etch (DEDE) has the disadvantage that overlay errors cause CD errors, but the processes are known.

To save some of the cost of DEDE, a lot of work is going into “freezing” the first pattern in resist, then imaging the second pattern, then etching the combined result. There are concerns about production cycle times, and there is a strong desire to keep the wafers in the photo-bay. This “freezing” technique clearly needs more work, but if litho toolmakers and maskmakers can hit the overlay tolerances, DEDE looks like the most likely process for the 32nm node.

Design tools are being developed to separate IC layouts into two complimentary mask patterns. Not all layouts can be automatically converted; some manual resolution of conflicts is required. The problem is similar to one encountered a few years ago when “hard” phase shift masks were introduced. There are new design check and simulation challenges, and it is clear that many IC houses now do full-chip simulation to find and alter “hot spots” in their designs — one paper at the IEEE litho workshop described how “warm spots” are also being identified in design using full-chip simulation. This is done, however, as a hedge for slight shifts of the process window on the production line — no one expects these software challenges to be a showstopper.

Our industry won’t make a clear process decision for the 22nm node for another couple of years, but the search for the best choice is underway, and at present there is no clear-cut favorite.

Super high NA [1.75 NA] optical systems do not look promising. Large LuAG crystals have been grown; but transmittance remains an issue. No good Gen 3 organic fluids have been found. The search has shifted to fluids doped with inorganic nanoparticles. Non-optical solutions may be required for the 22nm node.

EUV’s top problems, progress

The many champions of EUV point out that most “reasonable” projections for this technology show it will be less costly than double patterning, but EUV technology is not ready. The #1 problem remains the source power. Though both source suppliers reported good progress towards high power sources, both clearly feel the pressure of time — about 50X more power is needed, with about 18 months left before 22nm node decisions will be made.

The next big problem facing EUV development is a familiar but discouraging scenario: resist, which has been the pace-setting issue for 248nm and 193nm wavelength changes. Throughput models for EUV use optimistic sensitivity assumptions of 5-10 mJ/cm2. Linewidth error and line-edge roughness (LER) are serious problems — it looks like the resist roughness cannot be pushed below 3nm/edge. There were many good hallway discussions about likely causes, and a paper on molecular resist offered a promising solution, but in the end demonstrated no reduction of LER. SEMATECH has a major effort underway with member companies to collect and analyze the available data, in the hopes that the LER mechanism can be identified. Surface physics, not bulk properties, may be the cause.

Progress continues in the third pressing EUV issue, mask defects. The most numerous blank defects are now small pits in the blank surface. Work on the Synchrotron at UC/Berkeley is underway to look at EUV mask blanks with 13.5nm radiation to be sure there are no more undiscovered blank problems. Still, there is no large-area at-wavelength [13.5nm] defect scanner for controlling defects on EUV mask blanks.

Multibeam’s worldwide revival

Multi-beam direct write is enjoying a worldwide revival. The EC has launched a major program to push systems developed by Mapper and IMS to proof-of-concept tests and then bring one to production readiness. DARPA in the US has funded an effort at KLA-Tencor. Advantest has a multi-beam effort in Japan. Companies that make ASIC chips or small volumes of chips want a direct-write solution — design changes are so rapid for cell phone chips, for example, that these companies are pressing for a direct-write solution. The current throughput goal is 5 wafers/hr (300mm).

Answers in magnetic discs, FPDs?

One of this workshop’s attractive features is its multidiscipline structure and randomized topics, allowing the world’s experts in each technology to attend and discuss their work. This year’s workshop included several papers from the magnetic disc industry, where processes are moving to small features faster than ICs — by 2011 they will need a 27nm full pitch process [13.5nm half-pitch]. Electron-beam direct write (EBDW) probably will be used to pattern dots on a master disc. It is only necessary to e-beam pattern every other dot, and the patterns can be crudely made. Then a block co-polymer is applied on top of the EBDW dots. The block co-polymer self assembles in a manner that fills in the missing dots, and smoothes the cylindrical walls, so a good master can be made. This will then be replicated, probably using nanoimprint lithography. While work remains, the progress in the last 18 months has looked very good. IC patterning might borrow the block co-polymer process to improve LER for very fine patterns — in fact, the disc-drive people may have discovered the way to extend optics to the 22nm node.

While inkjet printing is not often discussed as microlithography, it was reported at this workshop that color filters in LCD-TVs are now being produced using inkjet printing. This technique offers cost savings so great that it is expected to replace proximity printing in most production lines. The nanoimprint technique being considered by the magnetic disc people also uses a form of inkjet printing to apply the fluid just prior to imprinting. Maybe the flat-panel learning curve can be transferred to nano-imprint lithography.

This conference is about potential solutions to support the pursuit of Moore’s Law; just which solutions will win will be decided by each company. The cross-fertilization of ideas at this workshop should shorten the time to success. By the next Lithography Workshop in August 2009, we should know what processes work best for the 32nm node, and what processes are in the lead for the 22nm node. G.R.


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