by Bob Haavind, Editorial Director, Solid State Technology
There were many novel device concepts explored at the recent 2007 International Electron Devices Meeting (IEDM) in Washington DC. While several papers discussed high-k/metal gate dielectric concepts to cut leakage currents, there was also some discussion of performance enhancement by using metal for the source and drain. A novel source/drain implant technique enabling very low leakage silicon-on-insulator (SOI) CMOS for 65nm and below was reported by IBM. A new concept for optoelectronic tweezers that can trap and move objects down to the nanoscale was described by Ming Wu of the U. of California at Berkeley.
Performance enhancement using metal source/drain was explored in two IEDM papers. Metal could potentially offer less S/D contact resistance, but the problem is high-contact resistance at the source/channel interface due to a Schottky barrier. Larrieu et al. from IEMN-UMR CNRS, STMicroelectronics, and UCL in France, showed how a low-temperature (<500°C) activation could be used for boron doping of PtSi source/drain in an implantation through silicide process that improved drive current by 50% compared to a dopant-free approach for thin-body SOI MOSFETs.
A Toshiba group showed how sputtering yttrium, ytterbium, and platinum onto an NiSi source and drain, and then annealing them to segregate the metals at the NiSi/Si interface can achieve 0.1-1.5eV Schottky barrier reduction for both nMOS and pMOS. The process is reported to be thermally stable and scalable, offering improved contact resistance for future metal S/D CMOS.
A number of junction engineering techniques were investigated by IBM research groups to lower leakage current for partially depleted, low-power SOI CMOS devices down to 10μmA/μm with a 1.2V supply voltage. These included low damage junction preamorphization implants, a high-energy halo, and drain-side tilted source/drain implants. The key advance in the work is a novel method to tie the body to the source of SOI devices without modifying the device layout. Tilted S/D implants from the drain side move the deep source region away from the gate edge and expose the body under the source-side extension for salicide (see figure). This internal source-body tie was achieved in both nFET and pFET by using suitable tilt angle and extension conditions. Both the subthreshold slope and drain induced barrier loading (DIBL) were improved, although there was some increase in channel resistance resulting in a penalty of about 5% in IDSAT.
Drain-sided tilted deep S/D implants in an SOI CMOS FET enable silicidization of part of the body near the source to tie the body to the source. (Source: IBM, IEDM)
Optoelectronic tweezers that could trap and move colloidal particles with diameters down to tens of nanometers were developed at the U. of California at Berkeley. The technique combines the advantages of optical tweezers and dielectrophoresis, but uses 100,000 times less power than optical tweezers, according to Ming Wu. Instead of handwired electrodes, the technique uses a projected light pattern on a photoconductive surface to create “virtual electrodes.” Since coherent light is not needed, low-cost sources such as a lamp or LEDs can be used instead of a laser. Light patterns are generated by a digital micromirror device are imaged onto the photoconductive surface, turning it into a programmable virtual electrode for DEP.
Wu reported that the technique has been used to trap single semiconductor nanowires, and also to manipulate cells in cell-culture media. — B.H.