by Debra Vogler, Senior Technical Editor, Solid State Technology

Several announcements involving Ponte Solutions during the last few months of 2007 illustrated a strategy of targeting DFM at the IP level by placing tools in the hands of designers where they are most comfortable: in the “cockpits” of their favorite EDA tools (e.g., Cadence’s Virtuoso platform, Pyxis’ Nexusroute yield-driven IC router, and Silicon Canvas’s Laker layout software). The company’s strategy is also grounded in the fabless/foundry business model. For example, to get ROI, a typical foundry would have to win as many as 1000 designs to get a return-on-investment, Michael Buehler-Garcia, Ponte’s VP of marketing and business development, explained in an interview with WaferNEWS. “That’s about 4X more than an IDM needs for the same size fab, but chasing so many designs means engagement with hundreds of companies,” he said.

With so many different designs and companies in the mix, though, the generic foundry design rules and DFM recommendations have to be very conservative. So Buehler-Garcia’s advice to the fabless companies is to own the DFM challenge. One way to enable DFM ownership is to provide designers of IP (e.g., standard cells, custom IP blocks, memories, etc.) with actionable critical-area analysis (CAA) information so that they can minimize the impact of the most critical CAA effects, as predicted by foundries’ certified defect kits. Interfacing Ponte’s YA System with Cadence’s Virtuoso platform and the pairing with Silicon Canvas’ Laker Layout software were two implementations of this strategy.

Sedrak Sargisian, VP of engineering at Ponte Solutions, explained to WaferNEWS that if an IP offering is “DFM-robust,” it can have an impact across multiple designs. “Whereas DFM corrections at the metal layers are generally applicable only for a specific design,” he said, “DFM analysis needs to be done as part of the overall design process, not only as a post place-and-route check.”

Also on Ponte’s plate has been its participation in the Silicon Integration Initiative (Si2). The company has been working with Blaze DFM (whose acquisition of Aprio’s technology was particularly significant) to deliver yield and lithography modeling elements to the Si2 specification. The company also is contributing to the Si2’s CMP specification with other Si2 members Praesagus and Cadence to synchronize their efforts.

Next on Ponte’s agenda is completing a physics-based etch modeling for vias/contacts and poly/metal. “The current rule-based etch bias can no longer ensure delivery of designs capable of being consistently manufactured in a nanometer fab,” said Ponte CTO Ara Markosian. “The impact of pattern density variability on etch-induced pattern transfer must be considered, accurately modeled, and corrected at 45nm and beyond.” Indeed, etch was listed as a critical concern moving into and beyond 45nm by all companies attending a recent DFM session held between the DFM Coalition of Si2 and various customers of STARC and the Common Platform, according to Jake Buurma, VP of operations at Si2.

The company’s etch solution was in beta evaluation with a major Japanese IDM during 4Q07, with additional evaluations to occur in this quarter (1Q08) when the product is released to the general market, according to Buehler-Garcia. — D.V.