Jan. 21, 2008 – STMicroelectronics has made its 45nm CMOS process available for prototyping via French brokerage service CMP to academia, R&D labs, and companies for multiproject wafer services, and has added its 65nm CMOS SOI process for academia. More than 100 universities (mostly in Europe) already have received design rules and kits for ST’s 65nm CMOS process, the group said in a statement.
“It is essential that university students and researchers can have access to the most advanced technologies, which we have been providing in cooperation with CMP for two decades,” stated Patrick Cogez, director of universities and external relations, frontend technology and manufacturing, STMicroelectronics. “Ensuring that universities have access to our leading-edge technologies also helps us to attract the best young engineers as part of our commitment to remain a technology leader on a long-term basis.”
CMP director Bernard Courtois noted that the total ICs designed in 90nm CMOS nearly doubled to 91 in 2007 (vs. 57 in 2006, and 32 in 2005).