Brion powers up to meet DPT challenges at 32nm-22nm

by Debra Vogler, Senior Technical Editor, Solid State Technology

Feb. 25, 2008 – At the opening of this week’s SPIE Advanced Lithography Symposium, Brion Technologies unveiled a more powerful version of its Tachyon Computational Lithography platform, and the release of Tachyon DPT, software that allows chipmakers to meet the low k1 requirements for memory and logic devices at 32nm and below.

Neal Callan, VP of product operations at Brion, described for WaferNEWS the four key elements of the new Tachyon 2.5 hardware platform: 1) an upgraded CPU from dual-core to a quad-core; 2) faster aerial image computations; 3) moving more compute-intensive operations from the CPU onto the FPGA, which is also faster than in the previous generation; and 4) improved system-level communication and data-flow optimization.

Just upgrading to a quad-core CPU would typically achieve 1.7+× improvement in speed. But with those four elements combined, Callan said the Tachyon 2.5 is able to get around 2.5× speed-up per rack, with the same IT footprint as the 2.0 version. “Typically, if it took you 12hrs to run a cm2 OPC job (whether creation or verification) on a Tachyon 2.0, that number would drop down to ~4-5hrs on a Tachyon 2.5,” he said. The 2.5 is bit-by-bit compatible with the 2.0 version, so if an end user runs the same job on each platform, and the difference of the two jobs is evaluated, they will be identical, because the fixed-point calculations are bit-by-bit compatible, according to Callan.

The Tachyon DPT software supports both types of double-patterning being used: the litho etch/litho etch DPT, or the computationally simpler spacer DPT. Callan noted that there are two components needed to be able to do DPT: coloring algorithms and overlay-aware model-based stitching. “You need to do coloring — i.e., be able to differentiate which set of the mask goes on mask 1, and which set goes on mask 2,” explained Callan. “The coloring algorithm resolves coloring conflicts on a full-chip level.”

The software is also layer-aware — for example, a mask is not split over a gate, instead the mask is split outside on a field where it’s less sensitive to overlay errors when the two masks are stitched back together. “When we stitch the two masks together, we have to make sure that they are less tolerant of the overlay shifts you get when you print one mask on top of another mask when there is an etch step in between,” said Callan. “A user can input a nominal mismatch in the anticipated overlay between the two masks and the software will take that into account when it stitches them together.” The software also provides for density balancing between the two masks.

The company is not disclosing how many customers it has for the new software, but Callan acknowledged that the company is engaged with several customers on DPT at 32nm — in particular, with memory manufacturers. Hynix was quoted in the product announcement. “Hynix recognizes the industry-leading performance of Brion’s Tachyon DPT solution,” said Dong Gyu Yim, research fellow, Hynix R&D division. “Double-patterning will be part of our low k1 imaging techniques and will be instrumental in our plans to begin producing devices at 32nm and below.”

On the logic side, the primary applications for the new software are at 22nm. Callan said that Tachyon DPT combined with the company’s existing Source-Mask Optimizer (SMO) provides a comprehensive 22nm-enabling solution for both R&D and production.

Tachyon DPT is currently available, and Tachyon 2.5 will be available in June of this year. — D.V.


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