Bulk silicon slims down: doing more with less

by Katherine Derbyshire, Contributing Editor, Solid State Technology

Feb. 1, 2008 – Recent interest in thin-film solar cells is driven in part by the high-cost limited supply of bulk polysilicon, the starting material for both integrated circuits (IC) and bulk silicon solar cells. The cost of polysilicon has more than doubled since 2004, due in part to rapid growth in the solar market. Long-term contracts currently price the material in excess of $70/kg, while spot market prices can exceed $300/kg. A standard bulk silicon cell consumes an estimated 10g of silicon per watt of peak output power. With module prices in the neighborhood of $4.80/W, silicon cost can be a significant part of that total.

The most obvious way to reduce silicon cost is to simply use less of the raw material. In ICs, the amount of silicon used by a given chip is already tiny, and Moore’s Law wedges the same functionality into a smaller area with each generation. For solar cells, in contrast, the area needed to produce a given amount of power is defined by the sun’s output and the cell efficiency. Reducing silicon area is not really an option. Instead, solar cells reduce their silicon consumption by getting thinner. According to Jef Poortmans, director of IMEC’s SOLAR program, manufacturers would like to reduce the silicon wafer thickness from approximately 200μm now to about 100μm by 2010.

Yet making thinner solar cells is not as easy as simply cutting thinner slices from the silicon ingot. Silicon is not a particularly good light absorber. Using less of it increases the chance that light will simply pass through without being absorbed.

Most cells use a reflective backplane — light reaching the backplane is reflected back into the silicon to increase absorption. However, the commonly used aluminum layer can itself act as a carrier recombination site. Instead, IMEC’s “i-PERC” (industrial passivated emitter and rear cell) design uses a dielectric passivation stack as a back reflector. Aluminum deposited through windows in this layer forms the back contact. While recombination can still occur, reducing the amount of aluminum in contact with the silicon reduces the number of traps and boosts efficiency.

Cells with small area aluminum contacts have been demonstrated before, both at IMEC and, using laser-fired contacts, at Germany’s Fraunhofer Institute. In the i-PERC, Poortmans explained, IMEC paid particular attention to the needs of an industrial process. For example, both front and rear contacts are deposited by screenprinting. Large area cells achieved 17.4% efficiency with silicon thickness <180μm, compared to 19% for small area cells with evaporated contacts.

At some point, conventional wire-sawn wafers simply won’t be able to reduce thickness cost-effectively. Kerf loss due to sawing already accounts for a substantial fraction of the total silicon consumed. Very thin (<100μm) wafers pose substantial handling challenges, too. It's likely that cells with active layers <20μm thick will be made by thin-film deposition methods.

However, the distinction between bulk silicon and thin-film designs blurs when, for instance, one possible approach uses metallurgical grade silicon wafers as the substrate, with an epitaxial device-grade silicon layer on top. This design reduces the silicon raw material cost


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