ISSCC: IMEC’s power-efficient converters, full-CMOS 60GHz antennae, EEG chip

Feb. 6, 2008 – At this week’s International Solid State Circuit Conference (ISSCC), European R&D consortia IMEC is pushing several new converter technologies built in 90nm digital CMOS, and encouraging more participants in continuing the work. It’s also showing a full-CMOS 60GHz antenna array, and a chip for small EEG machines.

Among the technologies are ultralow-power analog-to-digital converters utilizing patent-pending “successive approximation, flash, and “comparator-based asynchronous binary-search” architectures. Target applications include wireless SDR, 60GHz communications, and sensor networks. Notable statistics include a 7b 150M samples/s ADC with 22x improvement in power efficiency (0.89μW/MHz), and a two-step 7b 150M samples/s with record “figure of merit” of 10fJ/conversion step; a 9B 40M samples/s noise-tolerant SAR ADC with a 16% improvement in “figure of merit” (54fJ/conversion step). Last is a flash ADC with sampling speed >500M samples/s with 3x improvement in figure of merit (50fJ/conversion step)

Meanwhile, also at ISSCC, IMEC is showing a prototype 60GHz multiple antenna receiver with “several Gb/sec” rates at distances of up to 10m. The RF technology was built in standard digital CMOS to make it more cost-efficient to manufacture, and offer low power. The device contains two antenna paths, each with a low-noise amplifier and down-conversion mixer. A programmable phase shift of various incoming signals (enabling beam-forming) is realized on the same chip, to address the problem of high path losses at millimeter-wave frequencies. An on-chip quadrature voltage-controlled oscillator (QVCO) design combines the highest oscillation frequency with the largest tuning range ever reported in CMOS, IMEC reports.

The group says the device is the first step toward a complete CMOS-based phased array transceiver for 60GHz wireless personal area networks, making possible multi-Gb/s applications such as fast kiosk downloading and wireless high-definition multimedia interface (HDMI). Next step is to build four antenna paths using 45nm CMOS technology, and integrate other subsystems such as a phase-lock loop (PLL), analog-to-digital converter (ADC) and the patch-antenna array itself. IMEC will also begin initial experiments for a power amplifier.

Finally, IMEC says it has created a complete 200&mu’W 8-channel EEG acquisition ASIC with programmable gain and filtering, for miniature ambulatory EEG measurement systems. The device, fabricated in a 0.5μm CMOS process, incorporates an 11b ADC to digitize amplified and filtered EEG signals, a square-wave oscillator to generate the 1MHz clock for the ADC and a bias circuit. It also comprises calibration of readout channels and enables measurement of impedance of bio-potential electrodes, IMEC explained. The device measures 17.55mm2 and consumes only 200μW, translating to more than a month of operation from a standard coin cell battery.


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