by Ed Korczynski, Senior Technical Editor, Solid State Technology

In a paper to be discussed at this week’s International Solid State Circuits Conference (ISSCC), Intel and ST Microelectronics will show how they have pushed phase-change memory (PCM) technology to be able to demonstrate multilevel cell (MLC) devices.

Previously, Intel and ST Microelectronics had demonstrated 4Mb PCM arrays using a 180nm node line, and a 128Mb PCM device using a 90nm line. Now, Intel will show data demonstrating a 256Mb chip achieved though MLC programming. The process features nine copper interconnect layers with extensive use of low-k interlayer dielectrics for improved power and performance integrated with lead-free packaging. Any products based on this technology will come from the two companies’ Numonyx joint venture.

Justin Rattner, CTO of Intel, provided WaferNEWS with some insights into the development process, and the possible plans for this novel approach to PCM. “Using a rather novel programming algorithm, we apply a programming pulse and measure the electrical properties of the material to see how they’ve changed,” explained Rattner.

Based on changing the states of a chalcogenide material (Ge₂Sb₂Te₅, aka GST), PCM technology provides for very fast reads and writes at lower power than conventional flash and allows for more stable data retention — creating the potential to compete with leading memory technologies. The move from single bit/cell to MLC brings significantly higher density at lower cost/Mb.

GST, which has been investigated for decades, has the unique property of reversible phase change from crystalline to amorphous. For this to be useful as a memory cell, it has conventionally been considered that the change must be complete, but now it appears additional quasi-amorphous and quasi-crystalline phases have been created to allow for four levels/cell. “There’s been a feeling for some time that with an appropriate amount of programming control — and it’s an iterative programming algorithm with a series of pulses and verification steps — you can get it into intermediate states that are electrically distinct enough to accurately read out the state of the cell,” explained Rattner.

Like prior PCM architectures each bit is individually erasable, unlike NAND flash, which is only block-erasable. “The most ambitious thing you could think of for phase-change is to eventually replace DRAM,” opined Rattner. “Now we’re a long way from that, but the most ardent advocates for phase-change see that potential.” — E.K.