ISSCC: TI discloses 45nm details

Feb. 5, 2008 – At this week’s International Solid-State Circuits Conference (ISSCC), Texas Instruments is disclosing process and design information about its 45nm process-based 3.5G baseband and multimedia processor, which offers 55% better performance and uses 63% less power than the 65nm version.

In a paper presented today (Feb. 5), Uming Ko, TI Senior Fellow and director of the company’s wireless chip technology center, described the process, which utilizes immersion lithography and ultralow-k dielectrics, as well as other proprietary techniques including strained silicon, to double the number of chips produced on each wafer and to reduce leakage. TI says it started shipping samples of the devices in 4Q07, and expects full qualification later this year on 300mm wafers.

The device platform (using both low-power digital and analog) integrates hundreds of millions of transistors in a 12mm x 12mm package, according to TI, in a statement. It includes an ARM-based high-throughput communication and high-performance multimedia applications engine, high performance TMS320C55x digital signal processor (DSP), and an image signal processor, plus a number of integrated analog components including an RF Codec.

The device also incorporates TI’s upgraded SmartReflex 2 technology (first introduced at the 90nm node), with new capabilities including “Adaptive Body Bias” (automatic, dynamic voltage adjustment via forward body-bias and reverse body bias) “Retention ‘Til Access” memory (segmented memory to lower voltage), and “SmartReflex PriMer” tools (SoC design tools, e.g. to automate RTL generation).


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