by Bob Haavind, Editorial Director, Solid State Technology
by James Montgomery, News Editor, Solid State Technology
Feb. 27, 2008 – AMD and IBM say they have produced a working 22mm x 33mm test chip built with 45nm process technologies using EUV lithography for the first critical layer of metal interconnects, pushing beyond previous EUV efforts that involved “narrow field” portions of the design.
The work presented at this week’s SPIE, indicates successful integration of “full-field” EUV into the fabrication process across an entire test chip, the companies claim.
The test chip wafers first went through processing at AMD’s Fab 36 in Dresden using 193nm immersion lithography, then were shipped to IBM’s research facility at the U. of Albany’s NanoTech Complex, using ASML’s alpha EUV scanner to patter the M1 layer of metal interconnects. Transistor characteristics tested after various device-structure processes (patterning, etch and metal deposition, etc.) were “very consistent” with 193nm immersion-only test chips, the companies said in a statement. Additional metal interconnect layers will be added using standard fab processing to test large memory arrays.
Presenting results at SPIE, AMD’s Bruno La Fontaine indicated the SRAM chip (15GB in size) had the following characteristics:
– 5.3% 3σ and CDU 6.6%
– Overlay was 17.9nm x and 15.6nm y, but could be corrected down to 6.7 x and 5.9 y through flare concentration. CD control and overlay were “excellent.”
– Source power was 75W, ~1W at the wafer (vs. >200W for high-volume manufacturing).
– The resist had 3.75 mJ/sq. cm dose, and plenty of resolution for 45nm, he indicated.
– Defect levels were 1 defect/sq cm — vs. needs for 0.5 at 22nm, and an eventual target of 0.03.
In the SPIE presentation, AMD indicated it is targeting up to five critical layers (M5) to be processed with EUV, and is eyeing the 16nm node (2014 timeframe) for high-volume manufacturing.