IBM’s Starkey: The case for SOI won’t diminish w/ shrink

by Bob Haavind, Editorial Director, Solid State Technology

March 11, 2008 – Until the mid-1990s, SOI was considered too costly except for a few specialized niche applications, according to Starkey. Then, because of some advantages of the technology, IBM decided to go to SOI wafers for high-end servers, one of its key products. A number of factors drove the decision, he said, including better quality, narrowing of cost differences between SOI and bulk wafers, and the move to innovation rather than scaling to drive performance.

As IBM moved to 130nm, it added desktop PC processors and some printer controllers to the devices made on SOI wafers. Then, at 90nm, IBM won the competition to make SOI-based processors for all three major game consoles (Nintendo’s Wii, Sony’s Playstation, and Microsoft’s X-Box).

As the industry moves to 65nm and then 45nm, digital cameras may go to SOI, especially for portable miniaturized video devices, such as for high-definition or streaming video signals — rich-media applications for which SOI is particularly well-suited, Starkey said. In the future, handsets may go to SOI chips as well. At 45nm, he explained that all ASIC (application-specific IC) devices made by IBM will be on SOI.

As features have shrunk, more and more complexity has been required to make devices on bulk silicon, Starkey noted, so SOI processing has become less complex in comparison, while the price difference has narrowed. In bulk, large shallow trench isolation gets narrower at the top, making processing difficult, whereas SOI devices automatically have isolation that avoids latchup. Isolation is particularly important for analog circuits, he pointed out. Sometimes analog circuit islands are surrounded by an SOI layer, reducing self-heating.

The lower junction capacitance of SOI means that devices dissipate less active power — so for the same leakage, an SOI device can achieve about a 30% performance advantage over bulk devices, Starkey said. It is also possible to turn the performance advantage into circuits about 25% smaller using 20% less power, he said. At the same performance level, leakage can be 4×-8× less with SOI. In some applications, it is also possible to lower the supply voltage to achieve a power improvement. The lower power means less cooling is required, which can lower packaging costs.

On-chip DRAM (eDRAM) cell size can be reduced with SOI, making faster and less costly embedded memory. In fact, according to Starkey, eDRAM is being considered for SRAM replacement, because SRAM’s require a larger 6-device cell.

An additional advantage of SOI, he explained, making it especially attractive to the military, is less susceptibility to soft errors.

There also is an advantage for high frequency applications, Starkey said. Current-mode logic (CML) used for high frequency circuits is inherently leaky, so if conventional CMOS circuits using SOI can be used instead, there will be far less leakage.

Starkey said that IBM does not see the advantage of SOI diminishing as the shrink continues, as some have suggested. Instead he sees increasing problems with bulk transistors because of a well proximity effect. A resist edge comes closer to the device with each succeeding generation, he explained, and scattering off this edge is a growing problem. — B.H.

Click here for more presentations from the SEMI breakfast: Sitaram Arkalgud, head of SEMATECH’s 3D interconnect program in Albany, discussed the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics. Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.


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