Hermans leads accelerated MEMS development at IMEC

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There’s much more going on at the Belgian research center IMEC than the relentless pursuit of Moore’s Law and semiconductor process technology scaling. MEMS plays a big role in what IMEC calls its “More than Moore” efforts, centered in the CMORE program that leverages 200mm silicon technology for a range of “application-driven, heterogeneous integration” projects. IMEC’s main MEMS man is 20-year industry veteran Lou Hermans, who is strategic business director for new silicon technology applications. Hermans spoke with Small Times’ senior contributing editor Tom Cheyney about IMEC’s “monolithically integrated MEMS” approach.

Q: How would you describe MEMS’ place at IMEC?

Considering IMEC’s background, we are mainly focusing on integrated MEMS, a combination of CMOS and MEMS technology. Many years ago, we made a choice to start working on silicon germanium as a structural material. Since then we have been developing that technology, and we have several projects in place where we are using this technology for realizing or testing certain device structures.

Q: What are some examples of those devices?

In the early days, we made microbolometer arrays. Currently, we are working on micromirror arrays. We also have some projects on-going in the use of MEMS structures for memory-type applications.

Q: How would MEMS structures be used for memory?

I cannot disclose what we are doing exactly, but here’s a reference: what IBM is doing with the Millipede memory structures, where they use cantilevers to write, to make bits, and later on to detect bits or to erase bits.

Q: Since the 300mm fab became operational, have you had more access to the 200mm fab?

Yes. A few years ago, the 200mm fab was dominated by the scaling people, and most of the scaling work has moved to the 300mm facility, which gives us two things: Of course, we have more access to the line, but the line is also becoming more stable. In the past, the scaling people always wanted to have the latest lithography or deposition tools. This is not always what you want if you’re working on applications where you’re really making devices, where you’re working toward yield, so you would like to work in a more stable environment.

Q: Did you bring in any new equipment after the CMOS scaling guys left?

No, we already had in place additional tools needed for doing MEMS type of work. We have more access to some standard tools, because not everything we use is actually dedicated to MEMS. For example, we use standard CVD tools for SiGe deposition.

Q: Are you doing surface or bulk micro-machining?

Typically surface micromachining. In array-type applications you need the integration with the CMOS, because you have to individually control or lead out each of these elements. With a micromirror array, for instance, you have to control the position of each micromirror. The only way you can do this is by monolithic integration. Unlike other MEMS applications such as a single accelerometer or gyro, with arrays the hybrid approach is not a valid option.

Q: What efforts are underway for packaging?

We are working on wafer-level capping. Since MEMS are fairly sensitive structures, when you do the dicing, you have to protect them. We are looking into using SiGe for this. You actually grow the SiGe that you use for making the MEMS device, but at the same time you grow a cap, and then you do one release etch. Of course, there are still holes in it, which in the next step you have to close up. But instead of placing individual caps or a wafer of caps on top of a MEMS wafer, you do it in a layered deposition process that is compatible with the silicon processing environment.

Q: Since you’ve had more fab access, has there been an increase in MEMS interest and activity from the industrial partners?

There’s definitely a growing interest. We‘re now in a situation where we can better respond, but it’s also driven to some extent by the fact that some companies have stopped (or are considering stopping) their in-house scaling efforts, or are still doing scaling but only in cooperation with a silicon foundry like TSMC. But they’re also looking for new products that can run in these older fabs. So there’s an interest for diversification away from pure digital or analog circuits, to circuits with a higher added value, and MEMS is one option.


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