IBM, Hitachi ink 32nm dev pact

Mar. 10, 2008 – IBM and Hitachi say they have signed a two-year deal to research 32nm and beyond semiconductor technologies, particularly methods for analyzing devices and structures to improve characterization and measurement of transistor variation. They also indicated they hope the joint efforts pave the way to investigate even further transistor scaling. Work will be done at IBM’s Thomas J. Watson Research Center in Yorktown Heights, NY, and the College of Nanoscale Science and Engineering’s Albany NanoTech Complex.

“Hitachi’s cutting-edge semiconductor characterization capabilities, and IBM’s state-of-the-art CMOS research capabilities can help the two companies accelerate the pace of semiconductor innovation for the 32nm generation and beyond,” said Bernie Meyerson, VP of strategic alliances and CTO for IBM’s systems & technology group, in a statement. “By combining individual research strength and intellectual property we reduce the significant costs associated with research needed to advance the next generation of chip technology.”

“Hitachi’s significant expertise in analytical instrumentation and semiconductor physics can promote industry-leading research for next generation semiconductor technology,” added Eiji Takeda, VP and GM of Hitachi’s R&D group.


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