JSR touts “freezing material” for double patterning

Mar. 13, 2008 – JSR says it has achieved 32nm line and space patterns for 22nm node semiconductor devices with a new “freezing material” used in double patterning. Results were presented at last month’s SPIE Advanced Lithography conference.

The material is designed to harden the surface of the first material to prevent it mixing into the solvent of the second resist. The results are “the most wanted double patterning process achievable,” the company said in a statement.

Evaluation was conducted within IMEC’s advanced lithography industrial affiliation program, as part of the consortium’s sub-32nm CMOS research platform.

Double patterning is emerging as a likely choice for chipmaking at the 32nm node, but is one of several candidates to be adopted for the 22nm node,


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