BY HERWIG KIRCHBERGER, BIOH KIM, AND STEFAN PARGFRIEDER, EV Group
Technical process innovations in wafer-level packaging (WLP) have increased due to higher functional density, critical device real estate, an increase in market entry barriers, and stronger process integration capabilities.
In addition to redistribution, bump, and encapsulation technologies, novel concepts like molded reconfigured wafers are integrating single devices into alternative carrier materials at a wafer level. Standard key processes like thick resist lithography and metal deposition are complemented with wafer bonding and thin wafer handling technologies. True WLP concepts for MEMS that combine protection with interconnection in a single package are targeting through-silicon-via (TSV) technologies that require a conformal material deposition for via isolation at a lower cost. This has resulted in advances in production equipment.
Thick Resist Lithography and Spray Coating
Thick resist lithography processes like spin coating, spray coating, and full-field proximity mask alignment are being widely used in WLP technologies, for instance, to create redistribution and passivation layers as well as to structure the dielectric layers for under bump metallization and solder bumping.
The principle of full-field exposure requires a photomask accurately aligned to wafer targets in proximity. Simple exposure optics provide a large depth-of-focus and allow for thick resist exposure at large proximity gaps of 50-70 μm. Sidewall angles near 90° in the resist profile are achieved using high intensity 12" exposure optics. The one-step exposure provides a fully automated throughput of up to 140 wph. Redistribution and bumping of 200- and 300-mm wafers use minimum feature sizes in the range of 3-5 μm (Figure 1). A resolution target within this range is achievable with the latest mask aligners,* which perform precise print gap setting and wedge compensation to avoid contact between mask and wafer features. Precise optical edge bead removal can be implemented for electrical contact necessary for electroplating processes. Dummy bumps at the wafer rim that provide necessary uniformity of current distribution during electroplating process can also be integrated into the mask design. When using either positive or negative resists, the coating at the rim of the wafer can be maintained. This avoids metal deposition on the entire circumference, to seal the wafer during a subsequent electroplating process, and prevent backside contamination.
 Figure 1. 5/15µm Cu –high-aspect ration via exposed on a mask aligner. |
Efforts to coat uniform resist layers with a thickness range of 20 μm to 100 μm, where the thickness uniformity approaches ±1% of average thickness, have resulted in features added to spin coating and developing cluster tools. Even so, unavoidable resist loss through spin-off procedures and an inability to uniformly coat substrates with topographies is inherent to spin coating systems. A suitable alternative both for increased resist savings and for substrates with a high topography is spray coating.
The key to spray coating technology is an ultrasonic low-pressure spray nozzle. This nozzle oscillates to produce microscopic resist droplets. To achieve a proper distribution of droplet sizes, the viscosity of the material introduced to the nozzle must be below 20 cSt. Most commonly used photoresists and other chemicals can be diluted with solvents in the case when the chemistry is compatible with the base solvent. Once the droplets have been produced by the ultrasonic nozzle, they are accelerated toward the surface of the substrate via a stream of clean, dry air (CDA) or nitrogen. In terms of actual conformal coating performance, with substrates featuring a significant degree of topography, spray coating can achieve a thickness uniformity of better than ±10% Depending on the number of chambers, it is possible to reach a throughput of up to 60 wph including coating, developing, and baking.
While coating vertical features is common practice in MEMS technology, it has also recently been used in advanced packaging. TSVs are being used to interconnect the active front side of the wafer to the backside and further on to the pins of the specific WLP. A novel coating technology** has been developed, involving a two-step processes under special ambient conditions, that uniformly coats cavities having vertical sidewalls with aspect ratios up to 5 (depth/width) (Figure 2). This technology can be used to open features at the bottom of the deep cavity and uniformly apply dielectric coatings on the via sidewall for cheap, reliable, ductile electrical isolation.
 Figure 2. 60/200µm deep TSV coated using spray coating technology. |
Wafer Bonding Equipment
Widely adopted for transparent WLP applications like image sensors, digital mirror devices, and zero and first WLPs of MEMS devices, wafer-level bonding allows for smaller and thinner packages, improves yield due to higher cleanliness, enables the encapsulation of vacuum or process gas, and reduces packaging costs. High precision alignment of device wafer to cap wafer allows real chip-size packaging since the required width of the sealing rings is within the low micron range. Furthermore, different functional sub-systems like ASIC and MEMS can be processed on separate wafers, thereby greatly reducing the complexity and number of process steps. Vertical interconnects between wafers allow for 3D integration. The wafer bonding technique must be compatible with CMOS processing and with standard back end of line (BEOL) procedures. The bonding/annealing temperature is limited due to the stability of active devices on the wafers. Such bonding methods as Cu-Cu thermo-compression bonding, eutectic or solder bonding, plasma activated low temperature fusion bonding, and adhesive layer bonding are established 3D integration methods.
Tools have been developed for 300-mm wafer processing that incorporate an advanced bond alignment principle together with up to 4 wafer bond chambers. Post-bond alignment accuracy in the sub-micron range is achievable without having wafers that are transparent to infrared (Figure 3). The bond aligner is also able to perform high-precision-aligned direct bonding without transferring the aligned wafers to a separate high-force bond chamber. The bond chambers, designed for a plug-and-play upgrade in the field, come with a high force bond head up to 60kN, double-side heating up to 600°C, a 40°C ramp rate for heating and cooling, high-vacuum capability down to 1E-5mbar as well as a unique low-force wedge compensation system. This tool can be configured with both pre- and post-bond process modules like megasonic DI-water cleaning, intermediate bond layer coating, low temperature plasma activation, and high-resolution IR inspection.
 Figure 3. The principle of advanced face-to-face bond alignment for accuracies in the submicron range. |
Thin Wafer Handling Technology
To prevent thin wafers from being damaged during processing, they can undergo temporary bonding to a suitable rigid carrier substrate prior to the backside thinning process. The device wafer is bonded to a carrier wafer with its active surface using an intermediate adhesive layer that can be either a spin-on polymer or a dry-film adhesive. After backside processing, the rigid carrier substrate needs to be released. The adhesives allow the release of the device wafer using different approaches. UV release adhesives de-bond after exposure in UV light. Thermal release adhesives need to be heated above a characteristic release temperature, and solvent release adhesives have to be dissolved in a chemical solvent for de-bonding. Subsequent advantages of using a rigid carrier include the protection of the active surface of the device wafer during grinding/polishing procedures, the protection of the brittle wafer edge, and the flattening of strongly warped wafer materials.
 Figure 4. Generic process principle of temporary bonding and debonding. |
Fully automated temporary bonding equipment is capable of mounting the device wafer onto a carrier substrate with its active side facing the intermediate adhesive layer, thus preparing the device for secure and reliable back-grinding and backside processing steps. The intermediate adhesive layer can either be applied in a liquid form (wax or thick resists) via spin coating or in a rigid form (dry film adhesive tape) via fully automated lamination. After finishing the backside processing of the back-thinned device wafer, it can be de-bonded in a fully automated de-bonding system, which matches 25 wph throughput of the temporary bonding system. Depending on the type of de-bonding, the release of the device wafer is performed by heating up the wafer stack above the release temperature or exposing it to UV light. The thin wafer can be mounted on film frames or single wafer carriers as well as unloaded into a coin-stack shipment canister or cassettes.
Conclusion
Increased demand of production tools for next-generation WLP technologies have pushed equipment suppliers to improve established systems and introduce novel system concepts like thick-resist lithography and spray coating tools, wafer bonders, and thin wafer handling platforms. Advancements in equipment for production-worthy process solutions have been achieved. AP
HERWIG KIRCHBERGER, business development manager,; BIOH KIM, director of business development, AP and 3D interconnect; AND STEFAN PARGFRIEDER, business development manager may be contacted at EV Group, Dl Erich Thallner Strasse 1, A-4782 St Florian/Inn, Austria; +43/ 771253110; [email protected], [email protected], [email protected]