by M. David Levenson, Editor-in-Chief, Microlithography World
Second in a four-part series
Progress continued in EUV lithography, but at a rate well below that needed for insertion at 32nm. Bruno LaFontaine of AMD described the patterning of an entire metal-1 layer for a full exposure field AMD chip and the integration of EUVL into the process flow. While all the processing and diagnostics had not been completed, 45nm nMOS transistors on three wafers did work and showed low leakage. Since no OPC was required, the EUVL mask had only 5% of the data volume required for the 193nm reticle it replaced. Corners and other sharp features looked better on the resist image and ACLV was 5.3% (3σ). Raw overlay was better than 18nm. The flare had to be modeled and corrected using a rules-based biasing system that binned local circuit density into 4 categories. There were 1-2 defects/cm2 on the mask, none evidently critical. LaFontaine claimed that model-based OPC would get to 32nm and 22nm on the existing EUVL alpha-tools, and that an evaluation of capability for 16nm high-volume manufacturing (needed by 2014) would take place early next year.
Sources remain an issue. Based on extensive modeling done at Selete, K. Nishihara proposed a unique two-color laser-produced plasma (LPP) source that would achieve 5%-7% conversion efficiency when optimized. A 1.06μm wavelength prepulse vaporizes a tin droplet, producing a low-density target for a 10.6μm CO2 laser driver. A magnetic shield would protect the optics from the remaining fast ions. Nishihara claimed that a 10kW laser would be sufficient to get to 180W useful emission. The first two pulse experiments employed a foil, rather than a droplet, but doubled efficiency to 4%.
Martin Richardson of the U. of Central Florida remarked that long-pulse solid state lasers had shown 5% efficiency years ago, and that ion emission could also be reduced by doping the target and reducing the mass. He predicted that higher-efficiency laser pump diodes would improve sources based on solid-state lasers.
Thinking beyond the 32nm node, Katsuhiko Murakami of Selete suggested that 22nm circuits would require off-axis illumination with current exposure designs. Such a scheme had been shown to print 22nm lines and spaces in current resist by a team at Lawrence Berkeley Laboratory, but compatibility with circuit designs and full-field exposure tools has yet to be demonstrated. Winfried Kaiser of Zeiss suggested that the tool designs contemplated for 2011 and beyond would have larger numerical apertures and proposed a roadmap toward 11nm. — M.D.L.
Click here for the rest of the analyses in this package of SPIE writeups: a list of what’s still needed to enable 32nm generation chips printed with double patterning technology; litho projects (e.g. phase-shift and high-index immersion) that are falling behind the curve, and others that need a boost (e.g. imprint); and clever new technologies added to the equation, and what’s sparked an “arms race” among OPC and EDA firms.