SPIE report: Getting ready for double patterning…

by M. David Levenson, Editor-in-Chief, Microlithography World

(First in a four-part series)

“There are no new wavelengths. Everything on the roadmap will have to be made with a wavelength we have (193nm immersion or 13.5nm EUV) or with some dark lithography (like imprint or e-beam direct write),” an anonymous source told WaferNEWS, summarizing what seemed to be the main message of this year’s SPIE Advanced Lithography conference. “It is all cleverness and trickery now.”

Since high-volume EUV lithography is delayed, the first 32nm generation chips will have to be printed with double patterning technology (DPT) for critical layers and much of the conference focused on the various options, none of which seemed fully developed. Part of the problem is that anything you do to the chip after putting down the first pattern risks damaging that pattern, as Tom Wallow of AMD pointed out in a talk on DPT materials.

If DPT is to be the strategy, new materials with unlikely new properties might make all the difference. Current DPT methods either use conventional resists for two exposures and transfer the resist patterns into the substrate with two etch steps (so called “LELE” methods) or pattern a sacrificial spacer on which a hard mask is evaporated and processed before etching into the substrate. Since a second “cut mask” exposure is needed to define electronically useful shapes, these are termed “litho deposit litho etch” (LDLE) schemes. Materials exist for both of these and the LDLE has been shown to meet linewidth CDU specs, but the cost and complexity is high.

Lithographers would prefer material that could be processed entirely in the litho bay, or even better, on the exposure tool. Nonlinear resist would allow a wafer to be exposed twice with different patterns without one image erasing the other. No such materials have yet been proved to work, but the search continues.

For some applications, a two-tone resist may be enough. A single exposed layer of such a resist would be developed twice — once with a positive tone developer that would open features at the maxima of the image intensity, and once with a negative-tone developer that would remove material at the minima. Thus, resist would remain on the wafer only where the intensity was intermediate, either rising or falling, thus doubling the spatial resolution. Mireille Maenhoudt of IMEC claimed that such a process had been shown to work for NAND-like patterns. Another option coated a developed positive resist layer with negative resist, and then patterned that material, resulting in 50nm half-pitch lines, according to Maenhoudt. Other litho-cell-centric options included thermal and UV curing of the first pattern as well as “freezing” it by applying a barrier layer before spinning on the second resist.

Even when these methods achieve the desired resolution, subtle pattern distortions may occur, AMD’s Wallow pointed out. For example, he found a 173nm cure/bake step froze the first lines in place, but also caused reflow that changed the slope of line ends and tilted corners inward. Inspection with a top-down SEM will not be enough to qualify such processes for production, he warned. Still, he felt that processes with two litho steps (with some process in between) and a single etch (LPLE) would prove best economically.

Jo Finders of ASML elaborated an exposure tool roadmap towards 32nm and beyond, claiming that the current ASML XT:/1900i immersion scanner had demonstrated the needed 3-3.5nm overlay precision on multiple wafers and tools. Other contributions to CD uniformity could be fixed, he claimed, using the DoseMapper facility. With dipole illumination and LDLE methods, 32nm and even 22nm lines and spaces could be printed accurately enough.

Vincent Wiaux of IMEC described some of the anomalies that could be expected on a real chip. He reported that there is a narrow window between conditions that cause stitching between images to fail and those that cause unwanted bridging when k1=0.3 in the final DPT pattern. Thus, it is important to look for failure modes throughout the process volume. He found DPT design splits must either optimize for line/space resolution (in which case gaps between line ends would be large) or optimize the gaps and de-rate the linear resolution by ~15%. — M.D.L.

Click here for the rest of the analyses in this package of SPIE writeups: problems, yet promise, in development of EUV; litho projects (e.g. phase-shift and high-index immersion) that are falling behind the curve, and others that need a boost (e.g. imprint); and clever new technologies added to the equation, and what’s sparked an “arms race” among OPC and EDA firms.


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