by Griff Resor, Resor Associates, and SST Editorial Advisory Board member

Mar. 4, 2008 – With 38nm half-pitch seemingly the limit for single image 193nm immersion lithography, how will the industry reach the 32nm and 22nm nodes? That was the focus of last week’s SPIE Advanced Lithography conference in San Jose, CA. EUV teams from Zeiss and Nikon provided a peek at their plans for the 16nm and 11nm nodes. For the first time EUV appears to be in this race.

Still pushing optical lithography

Just one year ago, experts thought that even-higher-NA optics (1.7 NA) might be the next step for optical lithography. Now, however, it is clear that progress on the necessary materials has been too slow, and efforts to push NA to 1.7 seem to be floundering and will miss the 32nm window. Schott’s work on lens material LuAG has taken longer than planned, and current samples are not transparent enough to make lens elements. A significant investment is needed to scale up from 80mm to 250mm diameter. The key decision day has been moved to the fall of 2008.

The search for high-index fluids to replace water has utterly failed, with no suitable fluid found. Materials with high index (1.8) are near solid, not liquid. Hafnium nanoparticles are being considered as a doping material, but this feels far away in time. The search for a high-index resist has not been successful either.

Double patterning, on the other hand, seems to be working well. There are several ways to do double patterning and the alternatives are still being evaluated, but a double-litho, single-etch process may be the right solution. EDA firms are working hard to automatically divide one layer’s pattern into two complimentary mask patterns. “Color” conflicts are being resolved. It is possible to add overlap where needed. Checking design rules between these two masks is not that different than checking between two mask layers today. Full-chip simulators are being modified to manage the new complexity, and OPC models are being updated to manage the division of IC patterns to two masks. In fact, the sheer level of effort in the EDA community reflects their recognition that some form of double patterning will be the way this industry moves optical lithography to the 32nm node.

ASML, Canon, and Nikon discussed their overlay improvement roadmaps, with detailed overlay error budgets and descriptions of programs to tackle many parts of the budget. Based on their talks, it seems steady progress has been made, and one can only conclude steady progress will continue. Lithography tools are achieving 6nm overlay today, with champion data at 4nm — if this can be reduced to 2nm over the next two years, lithography tools will be good enough to permit double patterning. Designers might find a way to live with slightly larger overlay errors.

However, even champions of optical lithography showed that the cost of double patterning is high, and may be higher than EUV. A lot depends on the number of wafers printed from one mask. Obviously the largest companies will be able to enjoy a lower cost for double patterning than those who print fewer wafers/mask.

EUVL: Gaining momentum despite persistent challenges

There were many EUV sessions this week; all were standing room only. Clearly a lot of people in the IC industry want to see EUV succeed. They would like to have EUV for some layers of the 32nm node (early production in 2009), but they clearly want to use it at the 22nm node (for early production in 2011). Finer timing assumptions are made for NAND flash, DRAM, and logic, but this is still the general picture for toolmakers.

So when will EUV be ready? That was the big question this week. Three problems have topped the SEMATECH list for two years in a row: source, resist, and mask defects. There were separate sessions on all three topics.

Without at least a 100W EUV source (measured at the exit of the illuminator, the “intermediate focus”), EUV is not cost-competitive. The alpha tool at the U. of Albany is running with a 0.3W source, and just printed the first full-field exposure of a real chip. This tool will soon be upgraded to a 4W source. Both Cymer and Philips presented roadmaps that provide 100W sources, and Cymer plans to deliver the first such unit to ASML at the end of 2008. This is good news for EUV, but there are more assumptions than data in these roadmaps.

Most EUV resist images show an excessive amount of line-edge roughness, but images presented by the Berkeley National Labs showed very good 22nm line/space patterns, and their work demonstrates that a good EUV resist can be formulated. Resist has always been the pace-setting issue for prior wavelength changes — no matter how much work is done with small field optics, the final steps cannot be done without imaging on real production tools.

ASML is optimistic that the Cymer source roadmap will work. They claim 100W in a 30% duty-factor burst mode now, and high-powered EUV sources with 100% duty factor will be ready in 2009. ASML says it will ship five EUV systems starting in late 2009. So by 2010, IC companies can start refining their process using real EUV production tools. These deliveries will be in time to try EUV at the 32nm node and get ready for insertion into production lines at the 22nm node.

Picking a winner — but hedging bets

This is now a horse race. Double patterning will stretch optical lithography to the 32nm node, and might be used to get to the 22nm node. Though IC makers worry about cost and yield, EUV looks like it may provide competitive production tools in time for the 22nm node.

But not all IC makers are convinced — so this year’s SPIE also provided a renewed interest in e-beam direct write. Some see this as a hedge in case EUV does not advance as rapidly as planned. Others want a lower cost solution for low-volume manufacturing [ASIC chips]. In either case, the window has been opened again for e-beam direct write champions.

Optics with double patterning, EUV, or e-beam direct write for the 22nm node — which will it be? The answer will be clearer next year. But after 11 years as a doubting Thomas, I’m going to say the biggest IC companies will use EUV for the most difficult layers at the 22nm node. — G.R.