Stress-free Wafer Probing

Testing High Bump Counts with High Current without Burnt Probes, Scary Yields, or Substrate Damage

By Chuck Heebner, Robert Rogers, and Joseph Kuhn Wentworth Laboratories

Devices on sophisticated flip chip wafers have greater than 10,000 bumps, and are approaching upwards of 17,000 bumps. At test, these high bump count logic wafers require more power and have more I/Os. Fine-tuning the necessary probe card, probe and tester resources to successfully test at high current, with stable yields, and without a host of maintenance headaches, is daunting.

One company developed an ultra-powerful 48-core processor* that contained over 11,700 bumps and had power design requirements in excess of 120 amps — believed to be an industry first for flip chips. Within a 400-mm sq. footprint, a load of 85 kg of force @100 µm overtravel would be exerted during test.

Serious issues surfaced: How would it be possible to attain good alignment and planarity with a probe card, so that all contacts have good connection simultaneously in a planarity window that the prober can control, with 11,700+ contacts accepting high current without burning up? No off-the-shelf vertical probe card technology existed for this first-of-its-kind flip chip, nor was a tester’s power supply capable of supplying at least 120 amps of current. The prober had to accommodate the 85 kg of force exerted on the wafer with a safe performance margin. So many bumps concentrated in such a small footprint would induce significant amounts of compression and deflection throughout the system. Final yields had to be at high levels and sustainable, while minimizing repair and maintenance costs.

The 48-core processor required consideration of its 812 million transistors, a 90-nm low-k technology, more than 11,700 contacts at 175-µm contact pitch, 976 I/O and 10,700 power and gound contacts, a die size of ~20 mm on each side, and maximum power design requirements in excess of 120 amps. The probe card, prober, and tester resources initiated aggressive programs. Collaboration continued as the test program took shape.

The Probe Card

Once the processor design was locked, the next pressing issue was locating a probe card technology. One vertical probe card for flip chips** could accommodate more than 11,700 bumps, with each contact accepting 1 amp of current for 2 minutes and current bursts over 2 amps (Figure 1). In addition to meeting the current specifications, it could be used for successive generations of products.

Figure 1. Vertical probe card front view.
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An important consideration in choosing the probe card was its ease of repair. With traditional vertical technologies, replacing a contact in the center of an array would require timely and expensive disassembly. However, this novel contact technology could be swapped out without disassembly.

A standard probe card stiffener wouldn’t work. With 85 kg of force on the PCB, the stiffener needed to be thick, and have as many ribs to the center area as possible to minimize PCB deflection. The design was selected after reviews using different stiffener profiles and materials (Figures 2 and 3). The chip packages, multiple layer organic (MLO) interfaces or ‘space transformers’, were modified with the addition of gold to the pads to create a low resistance, long-life surface that mated to the probe card’s contacts. MLOs were then attached to the PCBs.

Figure 2. Custom stiffener for probe card.
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Figure 3. Chart illustrating prober compression minimized at high forces.
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An analyzer/metrology tool that could accommodate the 85 kg of force was selected to qualify the probe card. The probe card platform was customized to meet the high bump count requirement, to limit the force experienced by the prober to 1.8 gm/mil per contact. This kept it safely within the prober’s expected performance range. Upon verifying the probe card capability with in-house metrology equipment, 75-µm overtravel at the prober following last touch was recommended, plus an additional 2-µm overtravel to overcome planarity, and ensure good contact and minimal contact resistance.

The Prober

The recommended prober had a hot and cold chuck. Each part of the system contributed to the overall deflection in the prober (Figure 4). The prober compression included the tester interface, head plate, probe card, chuck deflection, chuck and stage compression, and horizontal stage displacement. Compression data on the probe card was collected to verify how much force was generated at 100-µm overtravel. A pneumatic piston/force transducer fixture gathered actual contact force and deflection curves to verify the probe card spring rate and prober force requirements.

Figure 4. Force vs. distance setup: 50 µm scales, 1/1000 lb. force gauge, pneumatic piston, vacuum bases.
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Important factors for selecting the prober included its ability to support high force with wide margin, good temperature control, and the availability of chuck performance data such as compression, deflection, and Z performance, particularly as Z approached the point of contact. This helpsed avoided burnt probes, decreased yields, increased repair costs, and PCB and substrate damage.

Another critical factor in the success of this project was the probe card cleaning. The probe card was cleaned at the start of each wafer, and at 2/3 of total overtravel. The load on the prober’s cleaning block, 56 kg, was higher than most probers could have accommodated.

The Tester

The test program to energize the flip chips had to apply a maximum of 1 amp to individual contacts to avoid contact fusing. With so many contacts and high current supplies, correctly setting the current clamps was essential. Each solution subset had to accommodate at least 120 amps, since more power would be needed to energize all the power and ground contacts during test. Significant changes to the hardware interface design were needed to meet high current demand with margin. Consequently, the tester selection needed customization Ultimately, the power supply was modified to high-current capable plugs, power planes on all PCBs were modified for higher current, and two 100 amp, high-current direct power supplies were ganged to supply up to 200 amps of current, providing a comfortable safety margin.

Essential Techniques to Ensure Success

In this particular case, testing all sections of the flip chip in parallel introduced higher current demand on supplies and higher heat generation due to simultaneous switching. To reverse these effects, subsections of the chip were progressively tested. As each section was tested, clocks to the remainder of the chip were shut off. This technique significantly reduced dynamic power. While static continuous power remained an issue, this too was reduced by testing at colder temperatures. Fully populating the probe card with all power and ground contacts reduced voltage drop, improving sort yield stability and resulting in higher prober usage.


Successful testing of high bump count flip chip wafers was performed at high current during production wafer sort, with impressive results. Many of the solutions will be able to handle multiple generations of products. In a brief state-of-the-art window, this project pushed the boundaries of force vs. deflection, and approached the limits of prober capability. AP

*Azul Systems’ Vega2 Multi-Core Processor

** Wentworth’s Accumax

CHUCK HEEBNER, technical sales engineer, ROBERT ROGERS, general manager, vertical probe card products, and JOSEPH KUHN, applications engineer, may be contacted at Wentworth Labs, 500 Federal Road, Brookfield, CT 06804; (203) 775-9311; Email: [email protected].

The Short Story

A flip chip first — a 48-core processor containing more than 11,700 bumps — created test issues not experienced in previous generations of multicore processors. An off-the-shelf solution didn‘t exist. Here‘s how a collaborative approach solved the problems, achieving stable yields in the process.

Watch-Out-For-It Checklist

  • Choose a probe card with the right combination of low grams/mil contacts and high current capacity.
  • Find a probe card that can accept high quantities of contacts that can maintain accuracy at the required contact count.
  • Consider how easily probe card repairs can be made, especially if needed in the center of the array.
  • Force seen by the prober = (# contacts in probe card) x (gm/mil of contact spring rate) x (average mils of OT). To qualify the prober, use this equation to calculate the total force of compression exerted on the probe card.
  • Clearly understand the deflection of the probe card and prober, and apply extra overdrive based on those deflections.
  • The most accurate way to define probe contact position is by adjusting Z height using the electrical first-touch method, since this will take into account the deflection in the system.
  • Analyze the probe card stiffener to ensure it can control excessive deflection of the PC board and probe card.
  • Identify a prober to handle the high force with a safety margin.
  • The metrology tool must also accommodate the force with margin.
  • Current clamps must be set properly based on the current capacity of the contacts, and the quantity of contacts to which the individual power supply is connected.
  • For high-contact count probing, multiple layer organic (MLO) thickness is important. In general, a thicker MLO provides extra stiffness and will reduce the likelihood of compression issues with the MLO.
  • Clean the wafer at the start of each wafer to reduce contact resistance.


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