“This is our unique way to offer a TSV solution,” explained Shlomo Oren, general manager of Tessera Israel. He says the company has developed a low-cost via-through-pad technology that can be done quickly on the entire wafer. Vias are created through the backside of the wafer to the bond pad without drilling directly through the silicon, Oren explained. The process avoids micro-cracks and is a stable, high-yield process. After the vias are formed, they are filled and electrical routing is formed. Using TSVs eliminates the need for metallization of the scribe lines, allowing for an additional 5% die per wafer due to increased usable wafer area.

(March 14, 2008) Atlanta, GA — The Georgia Institute of Technology (GIT) will be hosting the Industry-Academia Consortium Workshop on Nano Materials, Components, Packaging and Systems (NanoPack) on April 15, 2008, at the Microsystems Packaging Research Center at GIT in Atlanta, GA. For information and registration, go to www.prc.gatech.edu/events/nanopack.