by Bob Haavind, Editorial Director, Solid State Technology
March 11, 2008 – Progress toward 13.5nm extreme ultraviolet (EUV) lithography was covered by Gregory Denbeaux, assistant professor of nanoengineering, U. of Albany. Two types of sources, discharge produced plasma (DPP) and laser produced plasma (LPP) both currently work at low efficiency and generate large amounts of heat, and both require some type of debris mitigation. Power is still far below that needed for full production. EUV must be done in a very large vacuum chamber because the x-rays emitted by the target can’t penetrate air molecules. Current resists do not have sufficient sensitivity for the few photons that reach the wafer surface, so at 5 mJ/cm2 they currently operate close to the shot noise limit, Denbeaux said. Potentially there will be high line-edge roughness (LER) if the tools can not generate higher doses.
Defects could ruin the high reflectivity mirrors made of 80 alternating molybdenum/silicon layers, but so far SEMATECH has been able to stay on its target for defect reduction (see figure 1). Hydrocarbons contaminate the mirrors as well as the reflective mask and the optics, but keeping them out of the chamber is difficult because of outgassing from the resists. Some cleaning will be needed for hydrocarbon contamination, but oxygen or ozone are not good candidates because of potential oxidation. Atomic hydrogen cleaning is preferred instead, but this has not yet been well tested. Also, Denbeaux explained, there is no good way yet to monitor contamination on each mirror surface.
While much more power is desired, there is concern about heating as a result. Intense plasmas could distort mirrors and the collectors, and perhaps melt and fuse some of the molybdenum/silicon layers. To prevent this, he said, there needs to be better cooling behind the mask.
In spite of all the problems, Denbeaux said, EUV technology does work, although very far from a commercially acceptable level. He showed very good lines and spaces at 32nm and even below (see figs. 2, 3), and pointed out that AMD had successfully used EUV for the first metal layer of its Typhoon chip, as announced at the recent SPIE Advanced Lithography conference (see figure 4). Because of the need for double exposure/patterning at future nodes for 193nm tools, it turns out that if EUV targets can be reached in the next few years, it will provide a more cost-effective solution to advanced lithography — even though the tools might cost a cool $65 million each! — B.H.
Click here for more presentations from the SEMI breakfast: Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology. And Sitaram Arkalgud, head of SEMATECH’s 3D interconnect program in Albany, discussed the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.