Bonding Solutions for 3D Integration


Throughout the past several years, various bonding methods for use in 3D integration have been undergoing evaluation. Industry buzzwords include through silicon vias (TSVs), via first, via last, integrated solutions, and so forth. The encouraging news is that several products are starting to emerge from R&D and head for manufacturing. Currently, three technologies lead the way for wafer-to-wafer bonding for production applications. These include silicon direct or fusion bonding, adhesive bonding, and copper diffusion bonding. Each method has distinct limits and requirements for successful, high-yield bonds. Figure 1 highlights the diversity in approaches and range of interest in 3D processing.1 As indicated, there are some hybrid approaches as well, and companies continue R&D in this high-potential technology.

Figure 1. 3D wafer level bonding methods indicating major players, developers, and temperature regimes.
Click here to enlarge image

The requirements for 3D integration can be summed up by the statement, “alignment, alignment, and (did we mention) alignment”. The fundamental key of vertical integration is the ability to connect devices electrically across thin vertical distances rather than the lengthy lateral routing paths used in conventional 2D architectures. Thus the size and pitch of interconnects determine the requirements for alignment accuracy. Designs currently headed into production ramps for 2008 target 1-2 μm overlay registry with roadmaps heading toward deep submicron levels by 2010. A key factor that affects alignment accuracy is the temperature of the bonding process. Therefore, there is an inherent difference between the three leading methods. Superimposed on the thermal expansion issues are the differences in alignment methods, quality and type of alignment keys, and mechanical contributions of the equipment set.

Bonding Methods

Copper-to-copper (Cu-Cu) diffusion bonding is done by aligning two wafers face-to-face and bringing them into contact under vacuum or reducing environments. The wafers are then pressed together with 20-40KN of force and heated to 400-425


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