Freeze frame: JSR closes in on double-patterning at 22nm

by Debra Vogler, Senior Technical Editor, Solid State Technology

April 3, 2008 – During the recent SPIE Advanced Lithography Conference, JSR Microelectronics reported on its development of a “freezing material” for use in double exposure/double etch or double-exposure/single etch processes, achieving 32nm line and space patterns for 22nm node devices (see Fig. 1). The new material was evaluated on IMEC’s sub-32nm CMOS research platform, which is part of its advanced lithography industrial affiliation program. By using a material that freezes the first resist, it prevents the resist from either expanding or shrinking (i.e., CD growth), essentially cross-linking the resist. When the second resist layer is deposited, the two do not interact.

Mark Slezak, senior manager of lithography product development at JSR, told WaferNEWS that the new material is ideal for brightfield applications (i.e., line first double-patterning (DP) processes), so logic and some memory applications should be a good fit (see Fig. 2 and Fig. 3). The freezing material is not as useful for darkfield applications, i.e., most memory applications that are trench first. However, he noted that the concept works well for shrinking trenches in a litho, etch, litho, etch DP application.

Figure 1: Process flow of double-patterning with resist “freezing.”

According to Slezak, the materials breakthrough had to meet two requirements: 1) limiting the CD growth of the first resist pattern, and 2) limiting the interaction between the second resist pattern and the “frozen” first pattern. “When we first came up with this process, we saw CD growth of about 10nm, which put a lot of pressure on that first lithography layer,” Slezak told WaferNEWS. “We’ve been able to minimize that growth to ~1-2nm, so now, if the final goal is a 40nm line, we can image ~38nm and freeze it to a 40nm CD.”

Figure 2: Application example for a 32nm logic process. (Data courtesy of IMEC.)

Because the resists used to pattern both the first and second layers have the same solvent system, to prevent the second resist’s solvent from washing away the first resist, the properties of the first resist have to be changed before the second resist can be applied. “The first resist has to become non-soluble in the second resist’s own casting solvent,” said Slezak. “To do that, the polymer must be cross-linked so the first resist is no longer sensitive to photons in addition to not being soluble in the second resist’s casting solvent. The cross-linking avoids re-exposure during the second patterning as well as interaction of the second resist’s solvent with the first resist’s solvent.”

Figure 3: Application example for a 32nm memory process. (Data courtesy of IMEC.)

“By using a smart mask to decouple the two patterns that provide the final pattern, the freeze process is used to eliminate tight k1 lithography challenges,” explained Slezak. “In the case of a logic device, a logic pattern is broken up on the masks so the first patterning is done with mask #1 and the second pattern is done with mask #2, combining for a final pattern that eliminates the stress points (i.e., the low k1 imaging points).” — D.V.


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