Toshiba and Ponte Solutions team up on full-chip VCE modeling

by Debra Vogler, Senior Technical Editor, Solid State Technology

Apr. 14, 2008 – Earlier this year, Ponte Solutions’ VP of marketing and business development, Michael Buehler-Garcia, discussed its strategy of taking DFM to the IP level, and indicated the company was completing a physics-based etch model for vias/contacts and poly/metal. The need for such a model is a result of the impact of pattern density variability on etch-induced pattern transfer, which requires that the process be accurately modeled and corrected at 45nm and beyond.

At the time the story was written, Ponte noted that its etch solution had been in beta evaluation with a major Japanese IDM during 4Q07, with evaluations to continue into 1Q08. Now, with the release of news about the joint effort on March 31, the major Japanese IDM had a name: Toshiba, specifically, Toshiba’s Corporate Manufacturing Engineering Center (TCMC). The companies are working together to develop a via/contact etch (VCE) model.

The significance of the die-level etch process modeling, as Ponte’s chief scientist, Valeriy Sukharev, tells WaferNEWS, is that there has been a missing link between reactor (or wafer) scale and feature scale simulations of the etch process. Because there is a 6-7 orders-of-magnitude difference between the wafer size and a layout feature size, a die-level model is necessary as it provides a link between wafer-level and feature-level simulation tools, and a way to model layout-induced intra-die etch variations. Such a model is usable during the design and MDP (mask data prep) stage to reduce the impact of design/pattern density induced etch variability.

The full-chip VCE model addresses four key pattern-induced variations: 1) fluxes of neutral radicals, 2) etch rates, 3) CD variations, and 4) etch hotspots. “Once the latter are calculated for the full chip, our VCE can detect and report etch hotspots based on the fab defined thresholds of acceptable variations,” said Sukharev. He added that previous efforts to address non-uniform pattern density effects in etch processing at the design and MDP stages were rule-based. “But the more advanced the geometry, the more rules are needed. People tried to introduce proximity to first, second, and third neighbors, etc., and the amount of information and complexity kept growing.”

Sukharev noted that Ponte avoided the pitfalls of a rules-based approach by using across-die radical distribution considerations. “Combining these with the aspect-ratio dependent intra-feature radical transport resistance allows us to predict the layout shapes’ distortion caused by etch-assisted pattern transfer,” he said. “We do not need to introduce all the proximity factors separately.” He noted that all the information about the die layout is implicit in the solution, so there is no need for the analyzed etch step to be run on a specially designed test chip.

Ara Markosian, Ponte’s CTO, told WaferNEWS that the rule-based approach can also be used (and is currently used) as a “full-chip die-level” approach. “The point is that the rule-based solutions become insufficient for the 45nm node and below,” he said. “Only a few measurements are necessary to calibrate/tune the model to a process, which may translate to different savings depending on a fab’s turnaround time.” D.V.


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