450mm by 2012: Between the lines of PR lingo

by James Montgomery, News Editor, Solid State Technology

May 13, 2008 – Some of the biggest chipmakers are eager for a transition to 450mm wafers, because they see very attractive cost savings. And semiconductor equipment/materials firms are pushing back, still remembering the burden they bore for 300mm tool development and the lack of returns on that investment anywhere near what had been hoped. Some saber-rattling from both sides in the past year hasn’t helped both sides move forward, either — and that may be what’s behind the recent PR from Intel/Samsung/TSMC calling for a 450mm pilot line to be ready by 2012.

“They’re asking a little more nicely,” citing a desire to work with ISMI and the rest of the industry, and voicing a desire instead of a demand, notes Dean Freeman, research VP at Gartner. “That sets the forum up for a more healthy discussion.” Because for a 450mm transition to happen, both sides will need to participate, but the chipmakers will have to seed it, Freeman noted. “They won’t be able to demand, or even ask nicely, until they bring something to the table. ISMI tried to do a stronghold tactic last year, saying ‘We’re going to drive forward,” and the equipment people said, “You’d better rethink that!'”

A new, longer transition

Looking at the history of wafer-size transitions, Intel basically bore the expense for 150mm, and IBM did the same for 200mm. Equipment suppliers pretty much took the brunt of 300mm development, and by the time the tools were ready (and suppliers expected big returns) the 2001 downturn had arrived, meaning no one was buying any tools — even 200mm, much less 300mm. “Margins were terrible” until capacity tightened up again around 2004-2005, Freeman noted. Since then equipment suppliers have stuck to their guns, desiring more ROI on that 300mm investment before reinvesting in another wafer-size transition.

Despite statements from the chipmakers side about keeping to a ~10-year historical pace of change, the gaps between wafer-size transitions have been widening. “200mm stretched out further, and 300mm even further,” noted Freeman. The real metric, he noted, has been in a “crossover” from the previous wafer size to the next one. He added that a couple of years ago Gartner had pegged 450mm wouldn’t happen until 2017! That’s since been retracted to 2014-2016, but still several years out from the newly proposed 2012 due-date — mainly because the industry is now “in a period of poor profitability,” and the few companies who can afford 450mm will need to beef up revenue streams in the billions to afford it.

Intel has “confessed to backroom conversations with people” about 450mm tool development, Freeman noted, and a few firms already have come up with 450mm versions of chipmaking tools — e.g., handlers from Brooks and Asyst, and SES has a 450mm-specific single-wafer cleaning tool. Expect most of the initial 450mm tool designs to be similar to the Brooks tool that Freeman glimpsed at Semicon Japan: “Basically like a conventional 300mm tool on steroids,” with about the same footprint as existing tools so fabs don’t have to add more cleanroom space. Complaints from some suppliers to keep focusing on improving 300mm technologies could be “gamesmanship,” he suggested, noting that although there’s a significant development curve that has to take place, “there’s some learning some companies can use to get there faster.” For example, several tool companies (e.g. Applied Materials, TEL, Ulvac) could draw from lessons learned in LCD manufacturing, where smaller panels are roughly the same size (in sq. in), with similar uniformities in silicon and the oxide layers.

Two areas of 450mm progress

Assuming that the Intel/Samsung/TSMC PR is something of an olive branch, what progress should we expect and when, and where will the early signs show up first? A few areas will initially require a lot of work, particularly in wafer processing — e.g. figuring out the plasma density across a 450mm wafer, how to accurately flow gases, etc. “That will require modeling and experiments to make it happen,” Freeman said. A top concern is the thermal budget — what happens when you stress a bigger silicon wafer to temperatures and conditions required for (once 2012 rolls around) 22nm and 16nm-node manufacturing? Some of these questions are still somewhat guesswork even today for 300mm manufacturing. “We don’t even know what the specs are,” e.g. warp, polish, etc., Freeman noted.

And that’s where the first work will have to be done — establishing standards for 450mm wafer manufacturing and processing. Around 1996-1997 when first serious pushes for 300mm were taking place, “there was stuff going on in labs but also a lot of positioning and bickering and discussion at SEMI meetings, about what stuff should look like,” Freeman said. Similarly, look for a lot of 450mm discussions to crop up at upcoming SEMI standards meetings, e.g. to figure out wafer handling concerns, what a chamber looks like, how 300mm technologies can be scaled up, etc., “before anyone goes out and cuts metal.”

While modeling 450mm processes will be utilized early and often, much work will require real-world tests, which means getting actual 450mm wafers early and often. So that’s another place to look for early 450mm progress — the wafer suppliers. Nonsilicon stand-ins (e.g. glass and alumina) can be used for some physical tests (e.g., handling and testing), but “until you know what the yield is on a 450mm ingot,” with 100x repetition to ensure quality and statistical process control, “it’s kind of a moot point to charge forward with 450mm development,” Freeman said. Silicon utilization went down with the 200mm-300mm transition, and the 450mm transition “will see a lot more silicon waste,” he said, and “there’s only so much usable silicon” in a 450mm boule.

450mm costs: What’s at stake

The wafer segment also provides an early snapshot of what the extra upfront costs of 450mm might look like. The very first 300mm wafers cost ~$3k/wafer, roughly a 10x cost difference, then dropped to ~$1k when first production started, and have come down incrementally, noted Freeman — a bulk silicon wafer now sells for about $300; epitaxy is $300-$400, and SOI is in the $1000 range. (A 200mm bulk silicon wafer is ~$20-$30.) That same initial cost scale will probably be accurate for 450mm as well, he pointed out. “The first one who comes out with [a 450mm wafer] will charge a pretty penny” — maybe as much as $5k/wafer — until silicon suppliers come out and establish a consistent supply and 450mm development shifts into production.

So how much could a complete 450mm manufacturing environment cost? Freeman estimated $32B or more — ~$100M/toolset, vs. $60M/toolset for early 300mm toolsets — but he noted there really aren’t any reliable cost analyses yet beyond such “back-of-the-napkin estimates” (though adding that Gartner hopes to have a better estimate later this year with input from equipment makers). It’s nearly impossible to calculate how much could be saved over, say, ~20yrs of manufacturing with 450mm vs. 300mm because of so many variables in technology requirements for future leading-edge manufacturing. Today’s immersion litho tools cost $40M, for example, and by 22nm and 16nm new litho technologies are likely to be in the mix, at an as-yet undetermined (though most certainly sky-high) price — maybe $100M for an EUV scanner, for example. And that’s just for new litho technologies, let alone any other new processes that will have to be implemented at these far-reaching nodes.

Another big question mark: while there have been clear cost savings from 300mm vs. 200mm in terms of processes and operations (memory firms are selling off fully depreciated 200mm sites because they’re more expensive to upgrade/maintain than 300mm ones), will similar savings in terms of throughput and reduction in chemicals be realized at 450mm? “Will it be 30% cost savings off the bat? With so much up front [e.g. equipment and material costs], probably not,” Freeman said. “If we get 15% savings for the first fab, that will be looked upon very positively,” he said, “and then work it down from there.”

So with a 2012 deadline now on the table, how close to a 450mm pilot line are we today? “If the industry gets together and moves forward in the right direction — if it’s deemed economically feasible — then we can do it,” Freeman said. After a year of talking about it (2008), look for more action in 2009 and then 2-3 years of putting things together (2009-2011).

“It will take more cajoling, more pushing, and for some people, financial guarantees,” he said. “A lot of it depends on economics — and how good people’s negotiations skills are.” Top-tier suppliers in each category must be brought on board, with some sort of incentive; then others will follow, he said, creating an industrywide effort. “200mm and 30mm were very much individualistic; 450mm will be much more industrywide.” J.M.

Who really wants 450mm?

Intel and TSMC want 450mm “pretty quick” because die/wafer at 300mm means high edge losses and yield impact, while using bigger wafers will improve overall yields. They also claim bigger wafers will reduce manufacturing costs, though to what extent is still up for debate — “you can’t get equipment people to capitulate to 1.3x cost like they did to 300mm,” Gartner analyst Dean Freeman told WaferNEWS.

For Samsung, motivation for a move to 450mm is twofold: they can double the volume of DRAMs, and “basically pound a few nails in competitors’ coffins” — because the company is already building DRAM/NAND flash memory fabs that are in this ballpark investment scale.

Others who likely have an interest in a 450mm transition (but aren’t cited in the latest PR push): the Toshiba/Sandisk partnership. Toshiba is essentially becoming “Japan Inc.” by taking on other domestic chipmakers’ work (e.g., Sony). And Sandisk has interests for memory — for multiple 200,000+ WSPM facilities, production gains from 450mm are certainly attractive.

Others who probably are curious about, but not necessarily committing to, a 450mm transition: Hynix (from a volume manufacturing perspective), and Rexchip (the Elpida/Powerchip JV, also from a volume standpoint). Nanya/Micron might be considering a move, but probably not for a while, due to economics, Freeman noted, since they can still make memory with 300mm wafers and die sizes still ~90-150sq mm.

Freeman added that IBM could be interested in 450mm but its Common Platform Alliance would probably consolidate resources to build one such facility, but questions remain as to who would run it, where it would be located, etc. But while IBM probably wants 450mm for its systems-on-chip and ASICs as much as Intel and TSMC need it for logic, Freeman noted that IBM’s volumes in those areas don’t quite add up to makes sense for a 450mm fab. — J.M.


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