Chip heavyweights pin down 450mm date, tout “collaboration”

May 6, 2008 – Three of the world’s top chipmakers — Intel, Samsung, and TSMC — have agreed on a due-date of 2012 to have a 450mm-wafer-capable pilot line tested and ready — putting everyone in the semiconductor chain, from materials and equipment developers/suppliers to other chipmakers, on the clock to get 450mm technologies ready in four years.

The companies said in a statement that they chose the 2012 due-date because it keeps up with the industry’s “historical pace of growth,” though they also acknowledged the complexity of integrating necessary components with the transition will require “consistent evaluation” of that target timeline to “ensure industry-wide readiness.” They plan to cooperate with the rest of the industry to get all the necessary components and infrastructure ready by the target date, working with International SEMATECH (ISMI) and its coordination of industry efforts on 450mm wafer supply, standards-setting, and developing equipment testbed capabilities.

“There is a long history of innovation and problem-solving in our industry that has delivered wafer transitions resulting in lower costs per area of silicon processed and overall industry growth,” stated Bob Bruck, VP/GM of technology manufacturing engineering in Intel’s technology and manufacturing group. “We, along with Samsung and TSMC, agree that the transition to 450mm wafers will follow the same pattern of delivering increased value to our customers.”

“Increasing cost due to the complexity of advanced technology is a concern for the future,” added Mark Liu, TSMC’s SVP of advanced technology business. “Intel, Samsung, and TSMC believe the transition to 450mm wafers is a potential solution to maintain a reasonable cost structure for the industry.”

No specifics were offered about each partner’s level of participation in the partnership, except to state that “a cooperative approach will help minimize risk and transition costs.” That, perhaps, suggests that the answer to the biggest unanswered question — who will pay for it — means the tab will somehow be divvied up among the chipmakers asking for it and/or their suppliers tasked with making it happen.

The trio cite the well-known economies of scale enabled by an upgrade to 450mm wafers: >2x the silicon surface area of 300mm wafers, meaning a lot more chips/wafer, which will lower their production costs. They also cite more efficient use of resources (energy, water, etc.) with using the bigger wafers, citing benefits gained from the 200mm-300mm transition, which helped reduce emissions per chip of air pollution, and global warming gases and water.

While many in the industry have fought to maintain focus on improving 300mm productivity first, before exploring a transition to the next wafer size, the chipmakers state that the cost of 450mm R&D will be “substantially” reduced through aligned standards and “rationalizing changes” from 300mm infrastructure and automation.


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