Determining the Right Wafer Bumping Solution

By M.K. Chew and H.G. Su, Unisem-Advanpack Technologies
Wafer bumping is fast becoming the interconnect of choice for wafer level chip scale packages (WLCSPs). This migration is primarily driven by applications like power management devices, ASIC and memory chips, display drivers, Internet routers, microcontrollers, D/A converters, and RF devices that are transitioning from wire bond plastic encapsulated units to flip chips and WLSCPs.

Compared to traditional wire bond packages, wafer bumping offers attractive options that are essential for these shrinking devices packed with more functionality including:

  • Five times smaller footprint
  • Five times reduction in overall package weight
  • Four times better electrical conductivity
  • Four times better thermal dissipation
  • Ten times lower inductance
  • Interconnections that are mechanically more rugged
  • Lower packaging cost compared to die-level processing

    Depending on the package requirement, there are several wafer bumping options available in the market today.

    Gold Bumps
    With increasing power and operating frequency requirements, ball bumps are becoming a sought-after interconnect solution. Solder has been the traditional material for bumps, but the challenges with solder’s thermal and electrical capabilities have turned packaging designers toward gold bumps. Conductivity is the biggest advantage gold has over solder. Compared to solder’s electrical resistivity of 22 µ&#8486-cm, gold has a µ&#8486-cm resistance.

    Created using the plating, photo resist, and etch process, gold bump heights can vary between 5 &#181m and 25 &#181m. Current gold bump designs have a minimum under bump metallization (UBM) to passivation overlay of 5 &#181m, and a minimum passivation to bond pad overlay of 7 &#181m.

    Copper Pillar Bumps
    Copper pillar bumps consist of two segments &#151 a copper base and a solder tip &#151 and they can be constructed to a bump pitch of more than 100 &#181m. This unique structure helps copper pillar bumps overcome electromigration challenges that are typical in solder balls, especially at higher current densities. Similarly, copper pillar bumps display superior thermal capabilities as they can be placed closer together than solder balls, thereby increasing the number of contact areas for heat dissipation. Also, these pillar structures can be designed to form any shape and increase contact area to incorporate Faraday shielding. Compared to solder bumps, copper pillar bumps offer three times better thermal and electrical conductivity. With a standoff of more than 60 &#181m, copper pillar bumps allow for easy underfill and flux removal compared to solder options that have inconsistent and narrow gaps.

    Electroplated Solder Bumps
    Electroplated solder bumps are usually used in fine-pitch applications that demand a bump height between 25 &#181m and 100 &#181m, and bump counts of more than 3,000.

    During an electroplated solder process, a UBM is sputtered or evaporated over the entire wafer surface, adhering well to the bond pads and passivation layer. The UBM forms a good conductive layer for the electroplating currents. The electroplated solder bump is created through photo patterning, plating of the solder, striping of the photoresist and exposing of the solder, which is reflowed in the shape of a sphere. Since the plating process allows for smaller feature sizes and a higher level of precision, the soldered bumps can be constructed closer to each other than other methods of bumping.

    Ball Drop Processes
    These structures are typically used in applications that require a bump height of 140 &#161m to 330 &#161m and where the solder balls are larger, with diameters ranging between 160 &#181m and 400 &#181m. In a classic ball-drop bumping process, after the secondary photo resist is removed, a solder ball, generally with a material composition of SAC (SnAgCu), is mounted to sit on a Cu base and reflowed.

    Now that we have addressed some of the most common bumping options, let’s analyze certain critical factors that are essential to arrive at the right bumping solution.

    Bump Pitch and Height
    When choosing specific bumping options, it is important to determine the available bump pitch, the required bump height, and the choice of bump type based on the application requirement. For example, copper pillar and electroplated solder bumps support a pitch range between 100 &#161m and 800 &#161m, while gold bumps typically offer a pitch range of 30 &#181m to 150 &#181m and ball drops between 400 &#181m and 800 &#181m.

    While copper pillars can be constructed at pitch heights between 50 &#181m and 100 &#181m, electroplated solder bumps can be designed between 25 &#181m and 125 &#181m, while ball drops afford a greater height variation between 150 &#181m and 350 &#181m.

    Bump Count Per Wafer
    There is no limitation on the number of bumps per wafer as long as it meets the bumping process and the tooling design rule.

    UBM generally consists of the adhesion, diffusion barrier, and solder-wettable layers. The adhesion layer adheres to both the bond pad metal and the surrounding passivation layer, providing a strong electrical connection. While the diffusion barrier layer acts as a barrier restricting the diffusion of solder into the underlying material, the solder-wettable layer provides for easy adhesion to the molten solder.

    The reliability of the UBM is critical in determining the overall reliability of the package. Since the UBM materials and structures vary for different bumping technologies, the UBM strength and reliability need to be determined for each design and process.

    Redistribution Layer (RDL)
    RDL offers wafer bumping benefits to devices that are not designed for wafer bumping, including tremendous cost savings to IC manufactures who no longer have to redesign the whole die to reap the benefits of a WLCSP.

    RDL is a multi-photolithography process in which the signal path is re-routed from the die peripheral I/O to the desired bump location. Metal paths, often called runners or traces, are created to act as electrical conductors with dielectric layers in between to isolate them and minimize interconnect capacitance for high-speed application. It can also be used to create a coin for inductor applications and to shorten or lengthen the path for resistor applications.

    Several factors affect the cost of various bumping options. For example, ball-drop bumps are more expensive than other bumping solutions due to the high cost of the stencil tool. While bumping costs are directly proportional to wafer size, bumping technologies that are dependant on electroplating (like copper pillar and small bumps) tend to be more expensive because of the high plating costs.

    Passivation Polymers
    The passivation polymers used in wafer bumping depend on the kind of application and device requirements. For example, polyimide is the generally preferred polymer as it offers a wider process latitude. In high-frequency applications that require a low dielectric constant, benzocyclobutene (BCB) is more commonly used.

    According to Gartner, the WLCSP market is expected to increase from 8,905 million units in 2007 to 11,974 million units in 2011. As more of the wire bonding market transitions to WLCSP, package designs need to offer optimum wafer bumping solutions that meet the technology challenges of various applications while balancing the cost and efficiency expectations of IC manufactures. The above-mentioned bumping guidelines can be used to decide on the appropriate wafer bumping solutions while offering technology superiority and a lower cost of ownership to customers.

    M.K. Chew and H.G. Su, Unisem-Advanpack Technologies, No. 1, Persiaran Pulai Jaya 9 Kawasan Perindustrian Pulai Jaya 31300 Ipoh, Perak Darul Ridzuan Malaysia; [email protected]


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