Flash Memory for Stacked PoP Technology Issues and Test Challenges


Flash memory has become a fundamental building block in modern electronic systems. Package-on-package (PoP) stacking achieves the smallest package body size, mix-and-match logic with multiple memories, and flexibility of assembly. However, the flash memory integration in PoP introduces system reliability and test challenges at both the individual and stacked packaged levels.

With the rapidly growing semiconductor market, there is a demand placed on mobile appliances such as communications, computing, and entertainment. Electronic equipment manufacturers have increasingly required cost-effective non-volatile memory (NVM) solutions to maintain data or software codes. Low-cost NAND flash memory devices have filled this need and have established a vital position in the semiconductor industry. As a critical component in market-leading mobile products, including cellular phones, handheld computers and digital cameras, flash memories are one of the fastest growing market segments (Figure 1).

Figure 1. Revenue of memory shipped.
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Flash memory is the ideal candidate for integrated memory implementation because its content can be changed and updated in the field, providing flexibility required by modern systems. Therefore, the best approach is to use 3D packaging assembly technology, such as PoP configuration. A PoP stack can consist of a bottom package containing a high-performance logic device and a top package typically containing high-capacity or multiple memory devices. It provides a cost-effective and flexible solution, and has become an important feature for system manufacturers since they are able to select the top and bottom components from various sources.

However, the integration of flash memory in PoP introduces critical issues and challenges to systems, technology, and test.

NAND Flash Memory

NAND flash is gaining popularity in consumer products because it’s cheaper than conventional NOR flash. Effective evaluation of cost and reliability is crucial. For an effective estimation, the manufacturer should accurately evaluate the possibilities of flash memory offered in the markets and its capability to integrate on other packages.

Reliability is another critical constraint for non-volatile memory (NVM) in general, and even more for flash memory PoP. Integration with high-performance logic severely threatens flash memory reliability because of the compatibility between the memory and the logic controller. In particular, there are some specific technology issues to be addressed for a reliable PoP integration.

PoP Stacking

PoP technology vertically combines discrete logic and memory BGA packages. Two or more packages are stacked on top of one another with standard interface-to-route signals between them (Figure 2). The industry is focusing on this cross-section figure as the key technology.

Figure 2. Typical PoP structure.
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PoP stacking offers benefits such as reduced footprint on the PCB. Another important benefit is the minimized track and wire length between, for example, a controller and a memory. This results in better electrical performance of the devices. Furthermore, PoP provides great flexibility when selecting a memory device, chaining memory density, and sourcing the package supplier.

Figure 3. An example of package warpage.
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Increased market demand has determined the growth of stacked PoP technology. Since the top and bottom packages are usually from different suppliers, the assembly process has to be carefully selected to optimize and enable high yield because both the top and bottom packages experience warpage, which varies in reflow process (Figure 3). Note how some joints press down and are deformed, while another is being opened and collapses due to package warpage.

In a typical asymmetrical package, warpage can either be concave (smiling face) or convex (crying face). Warpage is the result of residual stress induced by non-uniform package shrinkage. Depending on the degree of polymerization during molding, application of external clamping force during the post-mold cure process can help to attenuate the effect of internal residual stress. The amount of package warpage changes with varying temperature, such as during reflow where the temperature typically reaches 260


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