This novel 3D-WLCSP package consists of a base wafer processed using conventional WLCSP techniques including an RDL and wafer-applied solder balls. The wafer-level RDL is designed such that a companion thinned die can be flip chip assembled directly onto the RDL between the WLCSP solder balls as shown in Figure 1. The package architecture consists of a base silicon wafer having I/O redistribution at the wafer level that includes flip chip interconnect pads for a mating die and solder balls for 2nd level interconnect. A thinned die is used to prevent 2nd level assembly interference. The thinned die is mounted onto the wafer using conventional flip chip techniques. Additionally, the base wafer can incorporate through silicon vias (TSVs) and one or both sides of the base wafer can include wafer-level redistribution technology. Figure 2 shows an example of a 3D-WLCSP partial wafer assembly. Both a conventional dispensed underfill material and process and a jetted underfill material and process (right) are shown.

(May 9, 2008) Endicott, NY &#151 The U.S. Department of Defense has awarded Endicott Interconnect Technologies, Inc.(EI) a $148.6M contract modification for the continuation of the current program to produce card frame assemblies including HyperBGA organic semiconductor packaging, multi-chip module assemblies, printed circuit boards, functionally-tested circuit board assemblies and engineering services in support of a high reliability, high-performance computing application. This contract modification period of performance is May, 2008 to December, 2008.