IDM economics at 32nm and beyond

by Ed Korczynski, senior technical editor, Solid State Technology

Masaaki Kinugawa, GM of Toshiba’s Oita operations, discussed the tough challenges faced by fabs developing advanced processes today. Both process technologies and device technologies continue to increase in complexity, and costs rise proportionally. Alliances to share costs, such as the IBM-centric one for bulk CMOS to which Toshiba belongs, are essential to continue IC shrinks to the 32nm node.

While the core bulk CMOS process is common, each of the partners in the alliance develops different optional processes and technologies to serve each of their targeted SoC markets. For example, Toshiba has invested in FeRAM and MRAM embedded memory with logic, MEMS, and through-silicon vias (TSV) for die stacking as power differentiators. Other optional technologies could include eDRAM, RF-CMOS, and sensors.

Even with careful management of process and technology development through the use of partners and alliances, owning a profitable fab is still getting to be very difficult. In the past, one process node in an IDM fab could be used over 10 or more years to manufacture a series of profitable products such as first SoCs then image sensors and finally MCUs. As the industry moves to 32nm and beyond, the sharply escalating costs of both IC product development and fab equipment may combine to slow down the historic chip cost reduction trendline.

The total cost to develop a chip product — including all EDA functions as well as maskmaking — has been nearly doubling each node from 90nm to 65nm to 45nm. Moving on to 32nm is projected to raise costs only ~50% over 45nm, but the absolute numbers are now making design-teams pause to consider their choice of manufacturing node. Kinugawa predicted that neither Japanese fabless nor customers nor IDM-internal designers are prepared to jump to the next node — such that a “several year gap” will appear between the availability of 32nm node fab capacity and substantial demand!

Only products with very high projected volume can enjoy the benefit of early access to advanced processes. With fab setup costs soaring, even well established IDMs need strategic fabless customers to take up some of the capacity. Toshiba expects that the majority of the initial volume for its 32nm node and beyond fab technology will come from fabless companies, before the established product migration from SoC to MCU finally begins. With a lot of new device materials and novel device structures, any fabless company interested in 32nm node chips will have to work intimately with its foundry. As a major IDM, Toshiba is ready to provide anything from traditional IC foundry work to full ASIC turnkey service including design help starting at the gate-level netlist, Kinugawa said. The company also claims to have 1000 engineers “for IDM foundry service.”

In some cases, a large IDM like Toshiba will also be differentiated from pure-play foundries by special capabilities, such as MEMS, sensors, and 3D techniques based on TSVs, for example.

For 3D packaging, Toshiba has taken aggressive steps to develop cost-effective die-stacking technology. The current offering is 60μm pitch micro-bumps which can be combined with die-thinning, flip-chipping, and wire-bonding to stack three layers of silicon. By 2010, the plan is to have 60μm thin silicon chips with TSV stackable on a silicon interposer for system LSI with lower power consumption and higher performance. Toshiba claims to have developed models such that stacked dice can be simulated as one chip for thermal analysis, power integrity, IR drop, noise, and ESD.

Whether automotive customers who need long-term commitments or consumer electronics customers who need advanced processes, Japanese customers are said to prefer Japanese fabs run by Japanese companies, Kinugawa noted. High quality and quick delivery are mentioned as decision factors, and the IDM may sometimes be able to establish bi-directional business for mutual benefit. The IDM foundry model is based on choosing a small number of key customers, and then servicing them with technology capability from design through test, assembly, and packaging. — E.K.


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