by Bob Haavind, Editorial Director, Solid State Technology
There will be a tough road ahead for lithography with double patterning and complex computation as well as requirements for more litho-friendly design, explained ASML’s Martin van den Brink, EVP of marketing & technology, speaking at the Next Generation Lithography session at The ConFab. This will be needed to enable low k1 193nm immersion lithography to push down to the 22nm node if extreme ultraviolet lithography (EUVL) is not ready by then.
The impact will vary considerably, however, depending on device type, he explained. NAND flash device patterns are simplest, with one-dimensional (1D) critical patterns for storage transistors. DRAM devices will be more complicated, with a transistor and storage capacitor having 1D and 2D critical patterns. The most complex will be SRAM and logic, with 2D critical patterns for six-transistor static RAM memory, and the most complexity for logic devices.
While a variety of double patterning, double exposure schemes are envisioned as the shrink continues, van den Brink showed a process sequence for one approach, briefly called litho-freeze-litho-etch, that should be lowest in cost since the wafer will not have to leave the litho cell between the two exposures. It involves a “freezing” process to retain an initial developed image, using thermal treatment, and then employs positive and negative resists to lay down a second pattern which can position lines in the spaces left by the first pattern. He commented that while this approach is in development, litho quality has not yet reached that required for 32nm performance.
For flash devices, van den Brink showed a spacer double patterning approach in which some initial CD (critical dimension) error becomes a pitch variation for the lines on the final pattern. By carefully doing an overlay-friendly layout for the spacers, some possible CD errors and potential bridging at sensitive areas can be avoided, he demonstrated.
The examples demonstrated how double patterning will require not just additional litho steps, but also will demand improved CD and overlay control. For example, a 7% CD error for single patterning with one process and one mask step, must be reduced to 3.5% for litho double patterning, with two mask and process steps, and to 3% for spacer double patterning, with 2-3 mask steps and 3-4 process steps.
He emphasized that pushing 193nm immersion lithography with low k1 factors (<0.4) will require a high level of integration of design and wafer processing integration. The entire array of RETs will be needed with design for manufacturing (DFM) techniques, plus application specific tuning and source-mask optimization along with litho-aware design constraints. Added techniques, such as correcting etch profiles through automated dose control, will also be required to keep CDs within tolerances. ASML has developed automated tools called DoseMapper and GridMapper to implement automated corrections for CD and overlay, he explained.
“Holistic” litho optimization will require an integrated combination of computational steps and model based predictive controllers linked to metrology in the lithography stages to achieve the tight CD and overlay tolerances that will be essential to making double patterning approaches successful, van den Brink concluded.
At the same time, ASML is continuing development of EUVL technology to enable the shrink to continue down to 10nm and beyond. He showed examples of devices made with current EUV exposure tools, which are still much slower than will be needed for acceptable throughput. Recently, he said, Cymer reported a significant improvement in the power generated by a laser power source, the type that will be used in future EUV tools. When asked what a commercial EUV stepper/scanner might cost, he said it would be “fifty or sixty million.”
“Is that dollars?” asked Ken Rygler, a consultant.
“No, Euros,” was van den Brink’s reply, adding that he didn’t want to get into a discussion of currency exchange rates. — B.H.