Mentor Graphics Addresses IC Implementation Challenges

(May 9, 2008) Wilsonville OR &#151 Mentor Graphics Corp. has aligned its integrated circuit (IC) implementation product lines under the design-to-silicon division to better address the design and manufacturing challenges of 45nm and smaller process nodes. The division, which will be headed by V.P. and general manager, Joseph Sawicki, will now include Mentor’s industry-leading IC products: the Olympus-SoC place-and-route system, the Calibre physical verification and DFM platform, and the design-for-test (DFT) product line.

(May 12, 2008) San Jose, CA &#151 Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter system. Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas credits the system’s memory capacity and fast turnaround time as the reason for the successful tape out.


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