Mentor, NXP to share DFT tools, technology, dev’t

May 6, 2008 – Mentor Graphics and NXP Semiconductors have announced a partnership whereby NXP will use Mentor’s design-for-test (DFT) products, including TestKompress compressed pattern generation and YieldAssist failure diagnosis tools, to improve its own test tools.

Such a partnership “is the most effective way to continue to meet our manufacturing test needs and to deliver the highest quality devices to our customers,” according to René Penning de Vries, SVP and CTO of NXP, in a statement. “First-time-right” is a crucial element of the manufacturing and design process, and the combination “allows NXP to use commercial DFT tools without disrupting any of our critical design projects.”

Mentor, meanwhile, obtains rights to NXP’s internally-developed test tools and technology, and a portion of NXP’s DFT tools development organization will join Mentor’s Design-for-Test product division (which is establishing a new R&D facility in Hamburg, Germany).

For Mentor, the new relationship “not only brings new DFT technology to Mentor, but also brings the talent of world-class DFT developers which will help us accelerate the development and delivery of innovative DFT technologies into the marketplace,” stated Joe Sawicki, VP/GM of Mentor Graphics’ design-to-silicon division.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.