by Debra Vogler, senior technical editor, Solid State Technology
May 21, 2008 – After the SPIE Advanced Lithography Conference earlier this year, there was a glimmer of hope in the eyes of some experts that EUV might be ready in time for 22nm half-pitch (follow the link to the Griff Resor video interview, in particular). At the ConFab event this week (May 20), Kazuo Ushida, president of Nikon Precision Equipment Co., told attendees that EUV was still the most promising solution for 22nm, and the only one that would keep the industry on track to meet the company’s estimated 17%/year reduction in total litho cost/bit needed to stay within historical guidelines.
Reviewing the lithography options going forward, Ushida noted that high-index immersion would not be ready in time for the 32nm node, and even if it were ready at 22nm (which is doubtful), double patterning would be needed, making that option very expensive. He presented critical layer reticle CoO data comparing double patterning lithography with EUV (see Fig. 1), showing that EUV reticle costs would be much less expensive than mask costs for double-patterning at either 32nm or 22nm.
Ushida also disclosed results using Nikon’s EUV1 tool installed at Selete in Japan, telling attendees that substantial progress has been made in achieving good line-edge roughness together with high sensitivity. “This data shows that in addition to recent progress on masks and light sources, EUV resists are also getting closer to their required performance,” he said.
Figure 1: Critical layer CoO at 1000 wafers/mask. (Sources: Nikon and SEMATECH)
Another slide based on Selete data showed some pattern data (dense lines, isolated lines, 45° patterns, and contact holes) printed on the Nikon EUV1 tool. “You can see from these images that 32nm pattern imaging is very good,” noted Ushida. Patterns at 22nm will require either an increase in NA or some simple RET (reticle enhancement techniques), he noted, “but the imaging will be very good as well.”
For 32nm hp, double patterning along with immersion lithography will be used. Ushida told SST that overlay (OL) errors have to be reduced by ≥50%, noting that the OL error budget includes more than just the litho tool, i.e., reticle matching and distortion from intermediate processes are also factors. One technique that he said has promise is pattern freezing technology (SST wrote about pattern freezing earlier this year from SPIE; TOK also has a process that uses negative and positive resist.) Because the use of pattern freezing eliminates the intermediate etch step, the company believes it will help achieve the OL requirement. He also noted the need for more accurate mask writers to achieve the required OL.
[In February, Nikon announced it will have a lithography tool for double patterning development ready by year’s end. Andrew Hazelton, executive staff, marketing department, Nikon Precision Equipment Co., told SST that the company’s production double-patterning tool in 2009 will achieve 3nm overlay and 180 wafers/hr throughput (125 shots/wafer). “As part of the double-patterning OL error budget, about 3nm is assigned to the lithography tool, and we currently specify 1nm for reticle matching error and 1nm for process factors,” said Hazelton. The process factors include distortion caused by the intermediate etch, and the slight change in wafer shape that occurs every time it is chucked in the exposure tool. “If pattern freezing is used, the intermediate etch step is eliminated, which greatly improves the chances of achieving the 1nm process budget.”]
Other alternatives that can be used while the industry waits for NGL include reducing the k1 factor to 0.28-0.30 for logic devices by using pattern restriction, custom illumination, and double-exposure (in lieu of double-patterning). For NAND flash memory in particular, Ushida mentioned Applied Materials’ sidewall process that enables pitch doubling.
Ushida concluded that there are enough options available now to extend current lithography technology to meet immediate needs, but EUV is the only promising solution for 22nm hp that is consistent with Nikon’s calculations that indicate historically, a 17%/year (for a two-year cycle) reduction in total litho cost/bit is necessary to keep the industry on track for continued the cost/bit reduction demanded by Moore’s Law (see Fig. 2).
Figure 2: Total litho cost/bit trend, assuming 9 critical 6 middle, 18 rough layers. Only litho costs are included; cost of double patterning may be underestimated. (Sources: Nikon, SEMATECH)
The information contained in Fig. 2 is based on joint work with SEMATECH and represents a worst case scenario of a DRAM with a lot of critical layers and a lot of low cost layers, which tends to highlight the critical layer costs. For a typical microprocessor layout there are a lot more expensive non-critical layers, so the critical layer cost is not immediately apparent, and the 32nm costs fall on the 17% line. For a typical NAND flash layout, the number of critical layers is very few, so they fall on the line as well, Ushida pointed out. Nonetheless, the data illustrates that in all cases, EUV is the most expensive at 32nm. — D.V.