Princeton tips way to “melt” chip features

May 5, 2008 – A new technique to literally melt away defects in etching microchip structures, and significantly reduce line-edge roughness (LER), has been revealed by scientists at Princeton U.

“What we propose instead is a paradigm shift: Rather than struggle to improve fabrication methods, we could simply fix the defects after fabrication,” said Chou, adding that fixing the defects could be “automatic, a process of self-perfection.”

Their method, dubbed “self-perfection by liquefaction” (SPEL), selectively melts nanostructures for hundreds of nanoseconds while applying a set of boundary conditions to guide the flow of molten material to resolidify into desired shapes, while natural forces (e.g. surface tension) smooth the structures into geometrically accurate shapes (e.g., straighter lines and rounder dots).

Simple melting by direct heat works with plastic but not high-melting-point metals in semiconductors — everything around the chip would melt too, and the process would widen and round off top and side surfaces. To address the first concern, they applied an excimer laser to heat only a very thin surface of the material for a millionth of a second, to melt only semiconductor and metal structures

To address the second issue (rounding), a flat plate was placed on top of the melting structures to guide the flowing liquid, preventing the molten structure from widening and keeping the top and sides flat and vertical.

A flat plate is used to guide the process, increasing sidewall slopes, flattening top surfaces, and narrowing the width while increasing the height. In contrast to conventional approaches, the guided melting process fixes all defects in a single, quick and inexpensive step.

They claim the SPEL process improved smoothness of 3-LER of 70nm wide chromium grating lines by 5x (see Fig. 1) — from 8.4nm to <1.5nm, "well below the 'red zone limit' of 3nm" laid out by the ITRS. Silicon linewidths were reduced from 285nm to 175nm, while height was increased from 50nm to 90nm.

Fig. 1. Electron microscope images show before (left) and after (right) examples. (Credit: Stephen Chou/Nature Nanotechnology)

Another benefit, dubbed a “surprise”: when the guiding plate is placed above the molten structures and not in contact with them, the liquid material rises up to touch the plate by itself — causing line structures to become taller and narrower (see Fig. 1). This creates “dramatically altered aspect ratios,” notes Donald Tennant, director of operations at Cornell U.’s NanoScale Science and Technology Facility, in a statement.

Fig. 2. The “Open” method involves using a laser to briefly melt defects, which self correct before cooling. The “Capped” method prevents the technique from rounding off the structures. The “Guided” version causes the structures to grow toward a nearby plate, causing them to become not only smoother, but also taller and thinner. (Credit: Stephen Chou/Nature Nanotechnology)

The researchers say the SPEL process can be extended to other metals and semiconductors, dielectrics, and large-area wafers. Chou and his group next plan to demonstrate the technique on 200mm wafers, saying that “several leading semiconductor manufacturers have expressed keen interest in the technique.”

The work, supported by DARPA and the Office of Naval Research, is discussed in the May 4 issue of Nature Nanotechnology.


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