Renesas Adopts Cadence Tool for Large Scale SoC and Flip Chip Design

“Given the complexity of this design and our aggressive schedule constraints, using a traditional ILM approach to hierarchical design was infeasible, and a new approach was required,” explained Miwa, adding that SoC Encounter’s hierarchical layout handling and ‘dynamic’ timing modeling technology coupled with its automatic floorplan synthesis and integrated flip-chip features allowed them to meet performance and schedule goals while reducing die-size and manufacturing costs.

(May 12, 2008) San Jose, CA &#151 Avago Technologies, supplier of analog interface components for communications, industrial, and consumer applications; announced what it believes to be a breakthrough in packaging technology that it says will provide a new level of design flexibility. Called WaferCap CSP, it is reportedly the industry’s first semiconductor-based chip scale packaging (CSP) technology.


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