by Pete Singer, Editor-in-Chief, Solid State Technology
A spokesperson for SEMI said unequivocally that equipment suppliers are not interested in pursuing a transition to 450mm wafers, and said there were “serious flaws” in the cost benefit analysis model that has been used to show productivity gains for the wafer transition. “A transition to 450mm does not make sense for the industry to pursue at this time,” said John Ellis, VP of global standards and technology at SEMI, speaking Wednesday (May 21) at The ConFab in Las Vegas. “It would be damaging for the industry. There is no net benefit for the industry.”
Ellis said SEMI formed a “Productivity Working Group” (PWG) in 2006, which originally looked at R&D funding gap problems — the gap between what equipment suppliers can spend on R&D and what it would take to remain on stay on the path defined by Moore’s Law. A study was commissioned an a report issued in 2005 by Ron Leckie of Infrastructure Advisors showing a “gap” estimated at $9.3B by 2010. [Full report downloadable from SEMI’s Web site here.]
Not only has the gap not been addressed, it’s actually widening — projected to be ~$10B/year by 2010, and $30-$35B by 2013. “The fact is we can’t fund everything.” Ellis said, noting that objective choices need to be made about where best to invest R&D dollars. “Technology advancement is the biggest lever we have,” he said. “That’s where we get the big gains that keep us on Moore’s law.” But he noted serious concerns about whether the industry can stay on that pace, and the impact of diluting R&D funding.
The original “Productivity Working Group” (JPWG) was a joint effort between SEMI and SEMATECH/ISMI. SEMI also later formed a separate Equipment Productivity Working Group (EPWG), whose members include Applied Materials, Tokyo Electron, Axcelis, KLA-Tencor, ASML, Lam Research, Brooks Automation, and others.
Ellis questioned the accuracy of historical data, noted several key trends that ran contrary to the push to 450mm, and dispelled several myths. He also questioned some of the key assumptions in the ISMI cost benefit analysis model.
Looking back at previous wafer size transitions, Ellis said there wasn’t much data on the 150mm conversion, but that there were no die cost improvements from the 150mm to 200mm conversion when doing an apples to apples comparison, referencing a 1998 paper published by Intel’s Dan Seligson.
More important, he argued, is analysis of the most recent 200mm to 300mm conversion. This generated a lot of improvements, but they “did not have anything do with the scale up in wafer size,” he said, citing as an example automated material handling “which we didn’t have at 200mm, at least not significantly,” Other advancements unrelated to wafer scale-up that helped improve productivity during that transition period included equipment throughput gains, reduced equipment footprint, advance process and equipment controls, and reduced facility costs via use of FOUPs. The cost/sq. ft of cleanroom space was lowered by >40%, from ~$6000/sq. ft to ~$3500, due to the use of FOUPS, Ellis said. “All these happened during the 300mm time period, but it didn’t happen because of the scale-up.”
Flaws in cost benefit model analysis
Ellis also openly questioned the validity of the common assumption that a transition to 450mm will result in a 30% improvement in productivity. He said the ISMI cost benefit analysis model that was used to generate that figure has “serious flaws” in the output multiplier expectations for beam tools such as lithography, measurement and inspection, and ion implant. The ISMI model predicts a 2.31× output multiplier for all tools, and roughly a 1.2-1.3× cost multiplier. A detailed analysis by SEMI’s PWG, however, put the output multiplier at 1.24, not 2.31 (see figure).
Figure 1: Analysis by SEMI members (ASML, KLA-Tencor, Axcelis) of beam-tool productivity multiplier expectations. (Source: SEMI)
Ellis said beam tools are unique in that they are constrained by the amount of area they can process per hour. “If you can only process so much area per hour and you increase the area, you reduce the number of wafers you can get through,” he said. With data showing nearly half the expected output multiplier as ISMI’s model, “this has a significant difference in the outcome,” he said. “Instead of saving 44% or so overall, we see that there’s no savings, for beam tools in particular.”
In addition to productivity output multipliers, SEMI’s PWG also looked at consumables usage, substrate costs, construction costs, and cost learning, and loaded all the parameters into the same cost benefit model used by ISMI. “Our analysis shows very little if any benefit to a simple 450mm wafer scale-up,” Ellis said. With no net benefit apparent, the group did not bother to explore R&D costs. “There’s estimates of R&D costs overall for the industry — $30B or so — but we decided to stop our analysis right there and really focus on next generation fab opportunities [defined by] 300Prime,” Ellis said. “We’re wrapping up our study.” Analyses should be posted on SEMI’s Web site in the next couple of weeks, and Ellis said input is welcomed.
Investments best made elsewhere
The PWG also analyzed where investments would have the highest impact for reducing cost for 22nm microprocessors. “There are some areas that are really unfavorable to scale-up,” Ellis said. Other areas seem favorable, e.g. plasma (PVD, CVD), “but if we look at them in proportion of the overall costs of the chip, it’s less than 10%,” he said.
Ellis noted several areas where there could be a big impact for the investment dollars, highlighting assembly, packaging and test as good targets.
Figure 1: Pinpointing the highest impact of investment dollars at the 22nm node. (Source: SEMI)
Another danger of a transition to 450mm is that technology development would stop on 300mm. “We can’t do both 300mm and 450mm,” Ellis said.
The timing of the transition was also raised, in relation to which technology node would be targeted. Ellis pointed to ISMI’s Industry Economic Model which targets the 32nm node for 450mm tools. “I can tell you right now that with 300mm tools in development for 32nm, we can’t do both. It can’t be at 32nm,” he stated. The 22nm node is when EUV lithography could come into play, but Ellis questioned what company would be willing to risk implementing 450mm and EUV simultaneously.
Cycle time could also become a problem with a transition to 450mm. “High-mix, high-volume is significant for a lot of companies,” Ellis said. “Our analysis shows that we can expect a 50% increase in cycle time for 450mm wafers.”
Perhaps one of the greatest dangers of 450mm is that it has become a distraction. “For the last two years, even though our group is going to be looking at a number of issues, we’ve been consumed with looking at 450mm,” Ellis said. He listed a number of productivity improvements — e.g., small lot manufacturing, single wafer processing, looking at setup time on tools — that can be implemented for next-generation fabs, “that we’ve not been able to look at in depth because of the 450mm issue. It’s a distraction for the industry. It’s going to distract from getting litho done.”
Ellis also dispelled several common myths about a 450mm wafer-size transition. First is that die size are driving the industry to 450mm wafers; he noted that die size is now “stable or decreasing. This is not a reason to move to 450mm.” It’s also a myth that wafer size diameter increases 50% every 10 years. “That’s just not true. In fact, as the pace of innovation slows down, we see the timing between wafer size increasing,” he said. Another myth is that, historically, wafer-size increases provide a 30% productivity improvement. “What we’re saying is looking at simple scale-up, in an ‘apples to apples’ comparison, that does not hold up,” he said.
Ellis concluded by calling for continued dialogue between chipmakers and suppliers. “We’ve been told by some chipmakers when we tried to continue the discussion that the ‘blue diamond decision’ has been made, the train has left the station,” he said. “Our concern is that nobody’s onboard. At least suppliers are not onboard, and there are a number of chipmakers that are not on board. We would like to back up the train and have some continued dialog.” — P.S.