SiP Seminar to Address Design Issues

The SiP paradigm allows the mixing of optimum active and passive device technologies in bare die format within a single package outline for cost-effective, high performance, short time-to-market functionality. It is suited for applications in a range of low, medium, and high volume electronics product applications. The addition of embedded passive component technology within such SiP modules also promises further performance, size, weight, and cost benefits. The technology has driven the development of robust design routes for right-first-time design and is now seeing volume applications for a range of communications and portable system products where cost-per-function, size, weight and performance are all critical factors.

The 8800 CHAMEO Multi Flip Chip Bonder from Datacon was developed for high-volume, high-throughput MCM / SiP assembly. Based on the same high-precision, dual-head architecture of its predecessor, the 8800 FC Quantum, it adds multi-flip-chip/MCM/SiP assembly and wafer handling capabilities as required in today’s advanced manufacturing environments.


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