Fujitsu tips low-power 32nm CMOS, power gating for system LSIs

June 18, 2008 – At this week’s VLSI Symposium in Hawaii, Fujitsu Labs and Fujitsu Microelectronics have tipped details on their development of lower-power CMOS technology logic LSIs that are “on par” with other 32nm metal gate technologies. They also say they have developed a circuit with <1μsec on/off switching to extend "off" times and reduce leakage current.

In the first disclosure, Fujitsu Labs says it has developed new technology for 32nm logic LSIs that lowers power consumption without degrading operating speed. It uses a conventional double-layer gate-electrode structure in the nMOS: a nickel silicide layer, and a silicon layer with impurities to add strain to the channel region and increase on-current. thus enabling operation with less power without degrading operating speed.

The pMOS gate electrode is fully silicided (with nickel) using high-temperature heat treatment and structure optimization; Fujitsu reports “no remarkable drops in performance due to depletion,” and so on-current can be increased and thus also enabling lower-power operation without degraded operating speed vs. 45nm logic LSIs.

Figure 1: 32nm-generation low-power CMOS technology. (Source: Fujitsu)

As a result of its work, Fujitsu says the new technology reduces operational power consumption by ~40%, lowering power-supply voltage without a drop in operating speed vs. 45nm logic LSIs. Furthermore, the number of new manufacturing process steps has been reduced from six to just one vs. previously reported 32nm metal-gate technologies, with a resultant cost increase of <1%. Future work will target applications for the low-power 32nm-generation technology.

New power-line trick drops restore time, noise

Meanwhile, Fujitsu Labs researchers also have come up with circuit technology that can rapidly switch on/off a power supply in <1μmsec, so as to extend the "off" period (sleep time) in order to reduce leakage current and lower power consumption.

As LSIs become more highly integrated leakage current increases, a problem particularly in mobile phones, which may idle for long periods of time with power supply on but no processor activity, which increases power consumption and lowers battery life. Power gating can switch off unused circuitry but with current capabilities it takes several μsecs to switch on/off — logically, shorter “off” (sleep) periods mean longer “on” times, and so more leakage and power consumed. In addition, turning the circuit on generates a “rush current” which creates power supply noise, requiring in a “stepwise” charging process. Rush current needs to be limited to just a few millivolts to avoid excess noise; but lowering restoration time to ~1μsec has required too-costly tradeoffs in lower power-supply impedance.

Fujitsu says its new technology employs a dedicated bypass power line, to which is connected the weak switch that typically controls the rush current, so the power-supply noise doesn’t affect the rest of the circuitry in operation powered by the primary power supply. Thus, power-supply noise over the power line when rush current is on is reduced to <25%, without lowering the impedance of the power supply -- and even with the same power supply noise, restoration time is <25% as long as before.

To solve this problem, Fujitsu connected the weak switch typically used to control the rush current to a dedicated bypass power line, so that the dedicated-bypass power-supply noise from the rush current doesn’t affect the rest of the circuitry in operation powered by the primary power supply. Thus, power-supply noise over the power line when rush current is on is reduced by >75% without lowering the impedance of the power supply; and even with the same power-supply noise, restoration time takes less than one-fourth as long as before.

Applied in a 90nm dual-core processor with two million gates, the resulting restoration time was 240nsec with power-supply noise reduced from 20mV to 2.5mV. Demonstrations suggested that power restoration time could be reduced to <1μsec, "a result that would have been difficult to achieve with conventional technology," the company said in a statement. Furthermore, chip area was only increased "a trivial" <1% with the additional dedicated bypass power line.

Future plans include incorporating the technology into Fujitsu’s CoolAdjust systematic power-saving technology, and adapting it to standard 65nm and 45nm CMOS targeting ASSP and ASIC applications.

Figure 2: Evaluation test results using a finished product chip. (Source: Fujitsu)


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